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Builder windows Build 4013 Microsoft Windows

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Input

Revision f1180b0c1f975149eb3a0774efba8f957b6247af

Infra

Steps and Logs

Show:
  1. ( 8 ms ) setup_build

    running recipe: “wasm_llvm”

  2. ( 9 secs ) bot_update

    [45GB/299GB used (15%)]

  3. ( 50 mins 55 secs ) annotated steps
  4. ( 59 secs ) Sync Repos
  5. ( 11 mins 1 secs ) LLVM
  6. ( 8 ms ) LLVM regression tests
  7. ( 28 secs ) V8
  8. ( 890 ms ) WABT
  9. ( 3 secs ) binaryen
  10. ( 31 secs ) fastcomp
  11. ( 3 secs ) emscripten
  12. ( 5 mins 8 secs ) emscripten (asm2wasm)
  13. ( 1 mins 4 secs ) emscripten (emwasm)
  14. ( 17 secs ) musl
  15. ( 3 secs ) compiler-rt
  16. ( 24 secs ) libcxx
  17. ( 38 secs ) libcxxabi
  18. ( 2 mins 14 secs ) Archive binaries
  19. ( 20 secs ) Compile LLVM Torture (O0)
  20. ( 3 secs ) Execute LLVM Torture (validate, O0)
  21. ( 25 secs ) Compile LLVM Torture (O2)
  22. ( 2 secs ) Execute LLVM Torture (validate, O2)
  23. ( 16 secs ) Link LLVM Torture (lld, O0)
  24. ( 15 secs ) Link LLVM Torture (lld, O2)
  25. ( 8 mins 49 secs ) Compile LLVM Torture (emwasm, O0)
  26. ( 17 mins 26 secs ) Compile LLVM Torture (emwasm, O3)
  27. ( 1 secs ) Execute emscripten wasm simd
  28. ( 29 secs ) Summary
  29. ( 0 ) recipe result

Timing

Create Thursday, 14-Mar-19 23:44:31 UTC
Start Friday, 15-Mar-19 03:19:10 UTC
End Friday, 15-Mar-19 04:12:47 UTC
Pending 3 hrs 34 mins
Execution 53 mins 37 secs

Tags

KeyValue
buildset commit/git/f1180b0c1f975149eb3a0774efba8f957b6247af
buildset commit/gitiles/llvm.googlesource.com/llvm/+/f1180b0c1f975149eb3a0774efba8f957b6247af
scheduler_invocation_id 9084397265520531776
scheduler_job_id wasm/windows
user_agent luci-scheduler

Input Properties

NameValue
$recipe_engine/runtime { "is_experimental": false, "is_luci": true }
branch "refs/heads/master"
buildername "windows"
buildnumber 4013
mastername "client.wasm.llvm"
repository "https://llvm.googlesource.com/llvm"
revision "f1180b0c1f975149eb3a0774efba8f957b6247af"

Output Properties

NameValue
$recipe_engine/path { "cache_dir": "C:\\b\\swarming\\w\\ir\\cache", "temp_dir": "C:\\b\\swarming\\w\\ir\\tmp\\rt" }
$recipe_engine/runtime { "is_experimental": false, "is_luci": true }
bot_id "swarm937-c4"
branch "refs/heads/master"
buildername "windows"
buildnumber 4013
got_revision "04600b4f26bdd5534788d437d0f82a5a47d97deb"
got_waterfall_revision "5fd6d5d2b27876f331efbda4b9ca5fc6294185ef"
mastername "client.wasm.llvm"
path_config "generic"
recipe "wasm_llvm"
repository "https://llvm.googlesource.com/llvm"
revision "f1180b0c1f975149eb3a0774efba8f957b6247af"

All Changes

  1. [CGP] add another bailout for degenerate code (PR41064)

    Changed by Sanjay Patel - spatelohnoyoudont@rotateright.com
    Changed at Thursday, 14-Mar-19 23:14:31 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision f1180b0c1f975149eb3a0774efba8f957b6247af

    Comments

    [CGP] add another bailout for degenerate code (PR41064)
    
    This is almost the same as:
    rL355345
    ...and should prevent any potential crashing from examples like:
    https://bugs.llvm.org/show_bug.cgi?id=41064
    ...although the bug was masked by:
    rL355823
    ...and I'm not sure how to repro the problem after that change.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356218 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/CodeGen/CodeGenPrepare.cpp
    • test/Transforms/CodeGenPrepare/X86/overflow-intrinsics.ll
  2. Tighten up tests that use -debugify as a shortcut. NFC

    Changed by Paul Robinson - paul.robinsonohnoyoudont@sony.com
    Changed at Thursday, 14-Mar-19 23:09:17 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision b1ceba26ca4c1c6571a64289d66e69f4796b5e28

    Comments

    Tighten up tests that use -debugify as a shortcut. NFC
    
    These now verify that a given instruction has a specific source
    location, rather than any old location. We want to make sure we
    propagate the correct locations from one instruction to another.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356217 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/Transforms/InstMerge/st_sink_check_debug.ll
    • test/Transforms/JumpThreading/branch-debug-info.ll
    • test/Transforms/SROA/alignment.ll
    • test/Transforms/SimplifyCFG/debug-info-thread-phi.ll
  3. [MC] Sort FDEs by the associated CIE before emitting them.

    Changed by Eli Friedman - efriedmaohnoyoudont@quicinc.com
    Changed at Thursday, 14-Mar-19 23:08:19 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision a092a834c4ce9e7f3e31fbefb0d7bbaef033e275

    Comments

    [MC] Sort FDEs by the associated CIE before emitting them.
    
    This isn't necessary according to the DWARF standard, but it matches the
    .eh_frame sections emitted by other tools in practice, and the Android
    libunwindstack rejects .eh_frame sections where an FDE refers to a CIE
    other than the closest previous CIE. So match the other tools and also
    sort accordingly.
    
    I consider this a bug in libunwindstack, but it's easy enough to emit
    a compatible .eh_frame section for compatibility with installed
    operating systems.
    
    Differential Revision: https://reviews.llvm.org/D58266
    
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356216 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/MC/MCDwarf.cpp
    • test/CodeGen/AArch64/arm64-big-endian-eh.ll
    • test/MC/ELF/cfi-signal-frame.s
    • test/MC/ELF/cfi.s
  4. MIR: Allow targets to serialize MachineFunctionInfo

    Changed by Matt Arsenault - Matthew.Arsenaultohnoyoudont@amd.com
    Changed at Thursday, 14-Mar-19 22:54:43 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision d8706fcd747d2129b2c00045dd8d8191b115f26a

    Comments

    MIR: Allow targets to serialize MachineFunctionInfo
    
    This has been a very painful missing feature that has made producing
    reduced testcases difficult. In particular the various registers
    determined for stack access during function lowering were necessary to
    avoid undefined register errors in a large percentage of
    cases. Implement a subset of the important fields that need to be
    preserved for AMDGPU.
    
    Most of the changes are to support targets parsing register fields and
    properly reporting errors. The biggest sort-of bug remaining is for
    fields that can be initialized from the IR section will be overwritten
    by a default initialized machineFunctionInfo section. Another
    remaining bug is the machineFunctionInfo section is still printed even
    if empty.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356215 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • include/llvm/CodeGen/MIRParser/MIParser.h
    • include/llvm/CodeGen/MIRYamlMapping.h
    • include/llvm/CodeGen/MachineModuleInfo.h
    • include/llvm/Target/TargetMachine.h
    • lib/CodeGen/MIRParser/MIParser.cpp
    • lib/CodeGen/MIRParser/MIRParser.cpp
    • lib/CodeGen/MIRPrinter.cpp
    • lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    • lib/Target/AMDGPU/AMDGPUTargetMachine.h
    • lib/Target/AMDGPU/LLVMBuild.txt
    • lib/Target/AMDGPU/SIISelLowering.cpp
    • lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
    • lib/Target/AMDGPU/SIMachineFunctionInfo.h
    • test/CodeGen/AMDGPU/scalar-store-cache-flush.mir
    • test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
    • test/CodeGen/AMDGPU/spill-before-exec.mir
    • test/CodeGen/AMDGPU/spill-empty-live-interval.mir
    • test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
    • test/CodeGen/AMDGPU/subreg-split-live-in-error.mir
    • test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
    • test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
    • test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
    • test/CodeGen/MIR/AMDGPU/machine-function-info.ll
    • test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
    • test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
    • test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
    • test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir
    • test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
    • test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
    • test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir
    • test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir
  5. [AArch64][GlobalISel] Add isel support for G_UADDO on s32s and s64s

    Changed by Jessica Paquette - jpaquetteohnoyoudont@apple.com
    Changed at Thursday, 14-Mar-19 22:54:29 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 4a50374b480f6aa06cf8175b694395937eaad82f

    Comments

    [AArch64][GlobalISel] Add isel support for G_UADDO on s32s and s64s
    
    This adds instruction selection support for G_UADDO on s32s and s64s.
    
    Also
    - Add an instruction selection test
    - Update the arm64-xaluo.ll test to show that we generate the correct assembly
    
    Differential Revision: https://reviews.llvm.org/D58734
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356214 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/AArch64/AArch64InstructionSelector.cpp
    • lib/Target/AArch64/AArch64LegalizerInfo.cpp
    • test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    • test/CodeGen/AArch64/GlobalISel/select-uaddo.mir
    • test/CodeGen/AArch64/arm64-xaluo.ll
  6. [AArch64][GlobalISel] Implement selection for G_UNMERGE of vectors to vectors.

    Changed by Amara Emerson - aemersonohnoyoudont@apple.com
    Changed at Thursday, 14-Mar-19 22:48:18 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 2e9c70af234f95958585555e8faf692024bb6715

    Comments

    [AArch64][GlobalISel] Implement selection for G_UNMERGE of vectors to vectors.
    
    This re-uses the previous support for extract vector elt to extract the
    subvectors.
    
    Differential Revision: https://reviews.llvm.org/D59390
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356213 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/AArch64/AArch64InstructionSelector.cpp
    • test/CodeGen/AArch64/GlobalISel/select-unmerge.mir
  7. [AArch64][GlobalISel] Add some support for G_CONCAT_VECTORS.

    Changed by Amara Emerson - aemersonohnoyoudont@apple.com
    Changed at Thursday, 14-Mar-19 22:48:15 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 751cb63424670a8c53e1dc937691af413eb4d772

    Comments

    [AArch64][GlobalISel] Add some support for G_CONCAT_VECTORS.
    
    Handles concatenating 2 x v2s32 and 2 x v4s16
    
    Differential Revision: https://reviews.llvm.org/D59390
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356212 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • include/llvm/Target/GlobalISel/SelectionDAGCompat.td
    • lib/Target/AArch64/AArch64InstructionSelector.cpp
    • lib/Target/AArch64/AArch64LegalizerInfo.cpp
    • test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir
    • test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    • test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir