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Infra Failure

Input

Revision a5cf8e0cbf048172792f491c025d2eed2aa079a8

Infra

Steps and Logs

Show:
  1. ( 6 ms ) setup_build

    running recipe: “wasm_llvm”

  2. ( 4 secs ) bot_update

    [36GB/232GB used (15%)]

  3. ( 6 days 9 hrs ) annotated steps
  4. ( 38 secs ) Sync Repos
  5. ( 58 secs ) LLVM
  6. ( 18 mins 45 secs ) LLVM regression tests
  7. ( 19 secs ) jsvu
  8. ( 634 ms ) WABT
  9. ( 1 mins 43 secs ) binaryen
  10. ( 11 secs ) fastcomp
  11. ( 4 secs ) emscripten
  12. ( 4 mins 36 secs ) emscripten (asm2wasm)
  13. ( 2 mins 36 secs ) emscripten (emwasm)
  14. ( 26 secs ) musl
  15. ( 3 secs ) compiler-rt
  16. ( 19 secs ) libcxx
  17. ( 14 secs ) libcxxabi
  18. ( 1 mins 22 secs ) Archive binaries
  19. ( 32 secs ) Compile LLVM Torture (O0)
  20. ( 4 secs ) Execute LLVM Torture (validate, O0)
  21. ( 43 secs ) Compile LLVM Torture (O2)
  22. ( 5 secs ) Execute LLVM Torture (validate, O2)
  23. ( 24 secs ) Link LLVM Torture (lld, O0)
  24. ( 23 secs ) Link LLVM Torture (lld, O2)
  25. ( 42 secs ) Execute LLVM Torture (d8, O0)
  26. ( 41 secs ) Execute LLVM Torture (d8, O2)
  27. ( 49 secs ) Execute LLVM Torture (jsc, O0)
  28. ( 47 secs ) Execute LLVM Torture (jsc, O2)
  29. ( 6 days 8 hrs ) Execute emscripten testsuite (emwasm)

Timing

Create Friday, 15-Mar-19 00:36:29 UTC
Start Friday, 15-Mar-19 04:38:31 UTC
End Friday, 15-Mar-19 08:39:00 UTC
Pending 4 hrs 2 mins
Execution 4 hrs

Tags

KeyValue
buildset commit/git/a5cf8e0cbf048172792f491c025d2eed2aa079a8
buildset commit/gitiles/llvm.googlesource.com/llvm/+/a5cf8e0cbf048172792f491c025d2eed2aa079a8
scheduler_invocation_id 9084393995715527600
scheduler_job_id wasm/mac
user_agent luci-scheduler

Input Properties

NameValue
$recipe_engine/runtime { "is_experimental": false, "is_luci": true }
branch "refs/heads/master"
buildername "mac"
buildnumber 4864
mastername "client.wasm.llvm"
repository "https://llvm.googlesource.com/llvm"
revision "a5cf8e0cbf048172792f491c025d2eed2aa079a8"

Output Properties

NameValue
$recipe_engine/path { "cache_dir": "/b/s/w/ir/cache", "temp_dir": "/b/s/w/ir/tmp/rt" }
$recipe_engine/runtime { "is_experimental": false, "is_luci": true }
bot_id "build207-m9"
branch "refs/heads/master"
buildername "mac"
buildnumber 4864
got_revision "04600b4f26bdd5534788d437d0f82a5a47d97deb"
got_waterfall_revision "5fd6d5d2b27876f331efbda4b9ca5fc6294185ef"
mastername "client.wasm.llvm"
path_config "generic"
recipe "wasm_llvm"
repository "https://llvm.googlesource.com/llvm"
revision "a5cf8e0cbf048172792f491c025d2eed2aa079a8"

All Changes

  1. [WebAssembly] Remove unused load/store patterns that use texternalsym

    Changed by Sam Clegg - sbcohnoyoudont@chromium.org
    Changed at Friday, 15-Mar-19 00:20:13 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision a5cf8e0cbf048172792f491c025d2eed2aa079a8

    Comments

    [WebAssembly] Remove unused load/store patterns that use texternalsym
    
    Differential Revision: https://reviews.llvm.org/D59395
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356221 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
    • lib/Target/WebAssembly/WebAssemblyInstrAtomics.td
    • lib/Target/WebAssembly/WebAssemblyInstrMemory.td
    • lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  2. AMDGPU: Remove intrinsic operand assert

    Changed by Matt Arsenault - Matthew.Arsenaultohnoyoudont@amd.com
    Changed at Thursday, 14-Mar-19 23:45:09 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision fab403b55c1fb99ee2a2398f4eea83a36b809dd3

    Comments

    AMDGPU: Remove intrinsic operand assert
    
    Before r355981, this was under LLVM_DEBUG. I don't think the assert is
    quite right, but this really should be a verifier check. Instcombine
    should not be asserting on this sort of thing.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356219 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
    • test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
  3. [CGP] add another bailout for degenerate code (PR41064)

    Changed by Sanjay Patel - spatelohnoyoudont@rotateright.com
    Changed at Thursday, 14-Mar-19 23:14:31 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision f1180b0c1f975149eb3a0774efba8f957b6247af

    Comments

    [CGP] add another bailout for degenerate code (PR41064)
    
    This is almost the same as:
    rL355345
    ...and should prevent any potential crashing from examples like:
    https://bugs.llvm.org/show_bug.cgi?id=41064
    ...although the bug was masked by:
    rL355823
    ...and I'm not sure how to repro the problem after that change.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356218 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/CodeGen/CodeGenPrepare.cpp
    • test/Transforms/CodeGenPrepare/X86/overflow-intrinsics.ll
  4. Tighten up tests that use -debugify as a shortcut. NFC

    Changed by Paul Robinson - paul.robinsonohnoyoudont@sony.com
    Changed at Thursday, 14-Mar-19 23:09:17 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision b1ceba26ca4c1c6571a64289d66e69f4796b5e28

    Comments

    Tighten up tests that use -debugify as a shortcut. NFC
    
    These now verify that a given instruction has a specific source
    location, rather than any old location. We want to make sure we
    propagate the correct locations from one instruction to another.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356217 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/Transforms/InstMerge/st_sink_check_debug.ll
    • test/Transforms/JumpThreading/branch-debug-info.ll
    • test/Transforms/SROA/alignment.ll
    • test/Transforms/SimplifyCFG/debug-info-thread-phi.ll
  5. [MC] Sort FDEs by the associated CIE before emitting them.

    Changed by Eli Friedman - efriedmaohnoyoudont@quicinc.com
    Changed at Thursday, 14-Mar-19 23:08:19 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision a092a834c4ce9e7f3e31fbefb0d7bbaef033e275

    Comments

    [MC] Sort FDEs by the associated CIE before emitting them.
    
    This isn't necessary according to the DWARF standard, but it matches the
    .eh_frame sections emitted by other tools in practice, and the Android
    libunwindstack rejects .eh_frame sections where an FDE refers to a CIE
    other than the closest previous CIE. So match the other tools and also
    sort accordingly.
    
    I consider this a bug in libunwindstack, but it's easy enough to emit
    a compatible .eh_frame section for compatibility with installed
    operating systems.
    
    Differential Revision: https://reviews.llvm.org/D58266
    
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356216 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/MC/MCDwarf.cpp
    • test/CodeGen/AArch64/arm64-big-endian-eh.ll
    • test/MC/ELF/cfi-signal-frame.s
    • test/MC/ELF/cfi.s
  6. MIR: Allow targets to serialize MachineFunctionInfo

    Changed by Matt Arsenault - Matthew.Arsenaultohnoyoudont@amd.com
    Changed at Thursday, 14-Mar-19 22:54:43 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision d8706fcd747d2129b2c00045dd8d8191b115f26a

    Comments

    MIR: Allow targets to serialize MachineFunctionInfo
    
    This has been a very painful missing feature that has made producing
    reduced testcases difficult. In particular the various registers
    determined for stack access during function lowering were necessary to
    avoid undefined register errors in a large percentage of
    cases. Implement a subset of the important fields that need to be
    preserved for AMDGPU.
    
    Most of the changes are to support targets parsing register fields and
    properly reporting errors. The biggest sort-of bug remaining is for
    fields that can be initialized from the IR section will be overwritten
    by a default initialized machineFunctionInfo section. Another
    remaining bug is the machineFunctionInfo section is still printed even
    if empty.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356215 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • include/llvm/CodeGen/MIRParser/MIParser.h
    • include/llvm/CodeGen/MIRYamlMapping.h
    • include/llvm/CodeGen/MachineModuleInfo.h
    • include/llvm/Target/TargetMachine.h
    • lib/CodeGen/MIRParser/MIParser.cpp
    • lib/CodeGen/MIRParser/MIRParser.cpp
    • lib/CodeGen/MIRPrinter.cpp
    • lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    • lib/Target/AMDGPU/AMDGPUTargetMachine.h
    • lib/Target/AMDGPU/LLVMBuild.txt
    • lib/Target/AMDGPU/SIISelLowering.cpp
    • lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
    • lib/Target/AMDGPU/SIMachineFunctionInfo.h
    • test/CodeGen/AMDGPU/scalar-store-cache-flush.mir
    • test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
    • test/CodeGen/AMDGPU/spill-before-exec.mir
    • test/CodeGen/AMDGPU/spill-empty-live-interval.mir
    • test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
    • test/CodeGen/AMDGPU/subreg-split-live-in-error.mir
    • test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
    • test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
    • test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
    • test/CodeGen/MIR/AMDGPU/machine-function-info.ll
    • test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
    • test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
    • test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
    • test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir
    • test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
    • test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
    • test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir
    • test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir
  7. [AArch64][GlobalISel] Add isel support for G_UADDO on s32s and s64s

    Changed by Jessica Paquette - jpaquetteohnoyoudont@apple.com
    Changed at Thursday, 14-Mar-19 22:54:29 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 4a50374b480f6aa06cf8175b694395937eaad82f

    Comments

    [AArch64][GlobalISel] Add isel support for G_UADDO on s32s and s64s
    
    This adds instruction selection support for G_UADDO on s32s and s64s.
    
    Also
    - Add an instruction selection test
    - Update the arm64-xaluo.ll test to show that we generate the correct assembly
    
    Differential Revision: https://reviews.llvm.org/D58734
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356214 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/AArch64/AArch64InstructionSelector.cpp
    • lib/Target/AArch64/AArch64LegalizerInfo.cpp
    • test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    • test/CodeGen/AArch64/GlobalISel/select-uaddo.mir
    • test/CodeGen/AArch64/arm64-xaluo.ll
  8. [AArch64][GlobalISel] Implement selection for G_UNMERGE of vectors to vectors.

    Changed by Amara Emerson - aemersonohnoyoudont@apple.com
    Changed at Thursday, 14-Mar-19 22:48:18 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 2e9c70af234f95958585555e8faf692024bb6715

    Comments

    [AArch64][GlobalISel] Implement selection for G_UNMERGE of vectors to vectors.
    
    This re-uses the previous support for extract vector elt to extract the
    subvectors.
    
    Differential Revision: https://reviews.llvm.org/D59390
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356213 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/AArch64/AArch64InstructionSelector.cpp
    • test/CodeGen/AArch64/GlobalISel/select-unmerge.mir
  9. [AArch64][GlobalISel] Add some support for G_CONCAT_VECTORS.

    Changed by Amara Emerson - aemersonohnoyoudont@apple.com
    Changed at Thursday, 14-Mar-19 22:48:15 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 751cb63424670a8c53e1dc937691af413eb4d772

    Comments

    [AArch64][GlobalISel] Add some support for G_CONCAT_VECTORS.
    
    Handles concatenating 2 x v2s32 and 2 x v4s16
    
    Differential Revision: https://reviews.llvm.org/D59390
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356212 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • include/llvm/Target/GlobalISel/SelectionDAGCompat.td
    • lib/Target/AArch64/AArch64InstructionSelector.cpp
    • lib/Target/AArch64/AArch64LegalizerInfo.cpp
    • test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir
    • test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    • test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir
  10. [llvm-strip] Hook up (unimplemented) --only-keep-debug

    Changed by Jordan Rupprecht - rupprechtohnoyoudont@google.com
    Changed at Thursday, 14-Mar-19 21:51:42 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 30e91d46e185a82e2421fd4b585ee39fe07aa534

    Comments

    [llvm-strip] Hook up (unimplemented) --only-keep-debug
    
    For ELF, we accept but ignore --only-keep-debug. Do the same for llvm-strip.
    
    COFF does implement this, so update the test that it is supported.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356207 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/tools/llvm-objcopy/COFF/only-keep-debug.test
    • test/tools/llvm-objcopy/ELF/basic-only-keep-debug.test
    • tools/llvm-objcopy/CopyConfig.cpp
    • tools/llvm-objcopy/ObjcopyOpts.td
    • tools/llvm-objcopy/StripOpts.td
  11. AMDGPU: Correct type for waitcnt debug flag

    Changed by Matt Arsenault - Matthew.Arsenaultohnoyoudont@amd.com
    Changed at Thursday, 14-Mar-19 21:23:59 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 487fd676cb65f1deb249748efc7e6f0eecba5e88

    Comments

    AMDGPU: Correct type for waitcnt debug flag
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356206 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/AMDGPU/SIInsertWaitcnts.cpp
  12. Add test I forgot to git-add in r356163.

    Changed by Adrian Prantl - aprantlohnoyoudont@apple.com
    Changed at Thursday, 14-Mar-19 21:23:52 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 506dd368898c25d2de214ae2d99e97d42a3e8017

    Comments

    Add test I forgot to git-add in r356163.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356205 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/DebugInfo/Generic/fortran-subprogram-attr.ll
  13. Line wrap README file

    Changed by Sam Clegg - sbcohnoyoudont@chromium.org
    Changed at Thursday, 14-Mar-19 21:09:14 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 2b070724f790512935b129b14a4035e9ce8a8b12

    Comments

    Line wrap README file
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356204 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • utils/vim/README
  14. [InstCombine] Add tests for range-based saturing math overflow; NFC

    Changed by Nikita Popov - nikita.ppvohnoyoudont@gmail.com
    Changed at Thursday, 14-Mar-19 21:06:46 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision d6add264d49e0f603803d76845bd3973df56ca7e

    Comments

    [InstCombine] Add tests for range-based saturing math overflow; NFC
    
    Tests for cases where overflow can be determined, but not based on
    known bits.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356203 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/Transforms/InstCombine/saturating-add-sub.ll
  15. [ARC] Add more load/store variants.

    Changed by Pete Couperus - petecoupohnoyoudont@synopsys.com
    Changed at Thursday, 14-Mar-19 20:50:54 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 48dc9cf87f3a93015ecccad29fcf36d22923a984

    Comments

    [ARC] Add more load/store variants.
    
    On ARC ISA, general format of load instruction is this:
    
        LD<zz><.x><.aa><.di> a, [b,c]
    And general format of store is this:
        ST<zz><.aa><.di> c, [b,s9]
    Where:
    
    <zz> is data size field and can be one of
      <empty> (bits 00) - Word (32-bit), default behavior
      B             (bits 01) - Byte
      H             (bits 10) - Half-word (16-bit)
    
     <.x> is data extend mode:
      <empty> (bit 0) - If size is not Word(32-bit), then data is zero extended
      X       (bit 1) - If size is not Word(32-bit), then data is sign extended
    
     <.aa> is address write-back mode:
      <empty> (bits 00) - no write-back
      .AW  (bits 01) - Preincrement, base register updated pre memory transaction
      .AB  (bits 10) - Postincrement, base register updated post memory transaction
    
     <.di> is cache bypass mode:
      <empty> (bit 0) - Cached memory access, default mode
      .DI     (bit 1) - Non-cached data memory access
    
      This patch adds these load/store instruction variants to the ARC backend.
    
    Patch By Denis Antrushin! <denis@synopsys.com>
    
    Differential Revision: https://reviews.llvm.org/D58980
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356200 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/ARC/ARCInstrFormats.td
    • lib/Target/ARC/ARCInstrInfo.cpp
    • lib/Target/ARC/ARCInstrInfo.h
    • lib/Target/ARC/ARCInstrInfo.td
    • test/MC/Disassembler/ARC/ldst.txt
  16. gn build: Add build files for clang-doc

    Changed by Nico Weber - nicolasweberohnoyoudont@gmx.de
    Changed at Thursday, 14-Mar-19 20:41:19 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision a41868aa77d86388c9f518c6a65f7810342c9678

    Comments

    gn build: Add build files for clang-doc
    
    Differential Revision: https://reviews.llvm.org/D59379
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356199 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • utils/gn/secondary/BUILD.gn
    • utils/gn/secondary/clang-tools-extra/clang-doc/BUILD.gn
    • utils/gn/secondary/clang-tools-extra/clang-doc/tool/BUILD.gn
  17. [InstCombine] remove duplicate tests

    Changed by Sanjay Patel - spatelohnoyoudont@rotateright.com
    Changed at Thursday, 14-Mar-19 19:41:21 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision b8324661573d880417cfd2faefb4f14420e85d6b

    Comments

    [InstCombine] remove duplicate tests
    
    These got accidentally doubled with rL356191.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356195 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/Transforms/InstCombine/fsh.ll
  18. Handle consecutive-double-quotes in Windows argument parsing

    Changed by Sunil Srivastava - sunil_srivastavaohnoyoudont@playstation.sony.com
    Changed at Thursday, 14-Mar-19 19:26:04 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 981d59612678a915da12b98a72739bb7e19b3a09

    Comments

    Handle consecutive-double-quotes in Windows argument parsing
    
    Windows command line argument processing treats consecutive double quotes
    as a single double-quote. This patch implements this functionality.
    
    Differential Revision: https://reviews.llvm.org/D58662
    
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356193 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Support/CommandLine.cpp
    • unittests/Support/CommandLineTest.cpp
  19. [InstCombine] canonicalize funnel shift constant shift amount to be modulo bitwidth

    Changed by Sanjay Patel - spatelohnoyoudont@rotateright.com
    Changed at Thursday, 14-Mar-19 19:22:08 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 82311c6556ecbe61cc471d366c23f4ae8eb49504

    Comments

    [InstCombine] canonicalize funnel shift constant shift amount to be modulo bitwidth
    
    The shift argument is defined to be modulo the bitwidth, so if that argument
    is a constant, we can always reduce the constant to its minimal form to allow
    better CSE and other follow-on transforms.
    
    We need to be careful to ignore constant expressions here, or we will likely
    infinite loop. I'm adding a general vector constant query for that case.
    
    Differential Revision: https://reviews.llvm.org/D59374
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356192 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • include/llvm/IR/Constant.h
    • lib/Analysis/InstructionSimplify.cpp
    • lib/IR/Constants.cpp
    • lib/Transforms/InstCombine/InstCombineCalls.cpp
    • test/Transforms/InstCombine/fsh.ll
  20. [InstCombine] add tests for funnel shift constant shift amount mod bitwidth; NFC

    Changed by Sanjay Patel - spatelohnoyoudont@rotateright.com
    Changed at Thursday, 14-Mar-19 19:22:00 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 74800bb68bc95e37b39d685f147e004976381764

    Comments

    [InstCombine] add tests for funnel shift constant shift amount mod bitwidth; NFC
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356191 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/Transforms/InstCombine/fsh.ll
  21. [MemorySSA] Remove redundant walker assignment [NFC].

    Changed by Alina Sbirlea - asbirleaohnoyoudont@google.com
    Changed at Thursday, 14-Mar-19 18:45:17 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision f63ee9026bec9f4f19a63b14e825ca53aec1ca6a

    Comments

    [MemorySSA] Remove redundant walker assignment [NFC].
    
    Subscribers: llvm-commits
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356189 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Analysis/MemorySSA.cpp
  22. [Tests] Add tests to demonstrate hoisting of unordered invariant loads

    Changed by Philip Reames - listmailohnoyoudont@philipreames.com
    Changed at Thursday, 14-Mar-19 18:06:15 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision d0d19c1992a6ee0ca8ff6f5f747a2a21ee2a1e76

    Comments

    [Tests] Add tests to demonstrate hoisting of unordered invariant loads
    
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356184 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/X86/hoist-invariant-load.ll
  23. [Tests] Revert an accident change to a test

    Changed by Philip Reames - listmailohnoyoudont@philipreames.com
    Changed at Thursday, 14-Mar-19 18:02:19 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 81c0530ed47c36dae505a4ec21435ec201a7bd8a

    Comments

    [Tests] Revert an accident change to a test
    
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356183 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/X86/hoist-invariant-load.ll
  24. [GlobalISel][AArch64] Add partial selection support for G_INSERT_VECTOR_ELT

    Changed by Jessica Paquette - jpaquetteohnoyoudont@apple.com
    Changed at Thursday, 14-Mar-19 18:01:30 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 1a446d1577d734d7e8f3e67ab8c72e9b6ced9a17

    Comments

    [GlobalISel][AArch64] Add partial selection support for G_INSERT_VECTOR_ELT
    
    This adds support for inserting elements into packed vectors. It also adds
    two tests: one for selection, and one for regbank select.
    
    Unpacked vectors will come in a follow-up.
    
    Differential Revision: https://reviews.llvm.org/D59325
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356182 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/AArch64/AArch64InstructionSelector.cpp
    • lib/Target/AArch64/AArch64LegalizerInfo.cpp
    • lib/Target/AArch64/AArch64RegisterBankInfo.cpp
    • test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    • test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir
    • test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
  25. Auto-generate an existing test to make it easier to update

    Changed by Philip Reames - listmailohnoyoudont@philipreames.com
    Changed at Thursday, 14-Mar-19 17:59:59 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 751d75d68309ba9fb2ddf49027f0344964ddfa46

    Comments

    Auto-generate an existing test to make it easier to update
    
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356181 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/X86/hoist-invariant-load.ll
  26. [ARC] Better classify add/sub immediate instructions in frame lowering.

    Changed by Pete Couperus - petecoupohnoyoudont@synopsys.com
    Changed at Thursday, 14-Mar-19 17:50:46 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 4385104c44f7189db633f82379f596dae90ff6e9

    Comments

    [ARC] Better classify add/sub immediate instructions in frame lowering.
    
    Summary:
    Some operations have multiple ARC instructions that are applicable.
    For instance, "add r0, r0, 123" can be encoded as a "LImm" instruction
    with a 32-bit immediate (8-bytes), or as a signed 12-bit immediate instruction
    for the case where the source and destination register are the same (4-bytes).
    The ARC assembler will choose the shortest encoding, but we should track
    the correct instruction in the compiler.
    This patch fixes the instruction used in some cases from ARCFrameLowering.
    
    Subscribers: hiraditya, jdoerfert, llvm-commits
    
    Tags: #llvm
    
    Differential Revision: https://reviews.llvm.org/D59326
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356179 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/ARC/ARCFrameLowering.cpp
  27. Speeding up llvm-cov export with multithreaded renderFiles implementation.

    Changed by Max Moroz - mmorozohnoyoudont@chromium.org
    Changed at Thursday, 14-Mar-19 17:49:27 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 3384c56bc0a6b2982282f8850af6c232ec98135e

    Comments

    Speeding up llvm-cov export with multithreaded renderFiles implementation.
    
    Summary:
    CoverageExporterJson::renderFiles accounts for most of the execution time given a large profdata file with multiple binaries.
    
    Proposed solution is to generate JSON for each file in parallel and sort at the end to preserve deterministic output. Also added flags to skip generating parts of the output to trim the output size.
    
    Patch by Sajjad Mirza (@sajjadm).
    
    Reviewers: Dor1s, vsk
    
    Reviewed By: Dor1s, vsk
    
    Subscribers: liaoyuke, mgrang, jdoerfert, llvm-commits
    
    Tags: #llvm
    
    Differential Revision: https://reviews.llvm.org/D59277
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356178 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • docs/CommandGuide/llvm-cov.rst
    • test/tools/llvm-cov/export_functions.test
    • test/tools/llvm-cov/showExpansions.cpp
    • tools/llvm-cov/CodeCoverage.cpp
    • tools/llvm-cov/CoverageExporterJson.cpp
    • tools/llvm-cov/CoverageViewOptions.h
  28. [InstCombine] add tests for funnel shift constant shift amount mod bitwidth; NFC

    Changed by Sanjay Patel - spatelohnoyoudont@rotateright.com
    Changed at Thursday, 14-Mar-19 17:39:40 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 587de2cafa83c6b8589655dcf77f9b7cf0bd3bc5

    Comments

    [InstCombine] add tests for funnel shift constant shift amount mod bitwidth; NFC
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356175 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/Transforms/InstCombine/fsh.ll
  29. [Tests] Add tests for reordering of unordered atomics on invariant locations

    Changed by Philip Reames - listmailohnoyoudont@philipreames.com
    Changed at Thursday, 14-Mar-19 17:36:58 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 4411e545d04a718904059d75a0cabbc226dc2788

    Comments

    [Tests] Add tests for reordering of unordered atomics on invariant locations
    
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356172 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/X86/atomic-unordered.ll
  30. Allow code motion (and thus folding) for atomic (but unordered) memory operands

    Changed by Philip Reames - listmailohnoyoudont@philipreames.com
    Changed at Thursday, 14-Mar-19 17:20:59 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 7747c1d2df876168611373f39f8513701f77e777

    Comments

    Allow code motion (and thus folding) for atomic (but unordered) memory operands
    
    Building on the work done in D57601, now that we can distinguish between atomic and volatile memory accesses, go ahead and allow code motion of unordered atomics. As seen in the diffs, this allows much better folding of memory operations into using instructions. (Mostly done by the PeepholeOpt pass.)
    
    Note: I have not reviewed all callers of hasOrderedMemoryRef since one of them - isSafeToMove - is very widely used. I'm relying on the documented semantics of each method to judge correctness.
    
    Differential Revision: https://reviews.llvm.org/D59345
    
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356170 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/CodeGen/MachineInstr.cpp
    • test/CodeGen/X86/atomic-non-integer.ll
    • test/CodeGen/X86/atomic-unordered.ll
  31. [Tests] Add negative folding tests w/fences as requested in D59345

    Changed by Philip Reames - listmailohnoyoudont@philipreames.com
    Changed at Thursday, 14-Mar-19 17:05:18 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 3b4378582808382fd4abfb57b51ec6e2ce77ee4c

    Comments

    [Tests] Add negative folding tests w/fences as requested in D59345
    
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356165 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/X86/atomic-unordered.ll
  32. [X86] Fix the pattern changes from r356121 so that the ROR*r1/ROR*m1 pattern use the rotr opcode.

    Changed by Craig Topper - craig.topperohnoyoudont@intel.com
    Changed at Thursday, 14-Mar-19 16:53:24 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 13b61457d35a5d694e994b5b2e5050a11199af9a

    Comments

    [X86] Fix the pattern changes from r356121 so that the ROR*r1/ROR*m1 pattern use the rotr opcode.
    
    These instructions used to use rotl with a bitwidth-1 immediate. I changed the immediate to 1,
    but failed to change the opcode.
    
    Thankfully this seems to have not caused a functional issue because we now had two rotl by 1 patterns,
    but the correct ones were earlier and took priority. So we just missed some optimization.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356164 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/X86/X86InstrShiftRotate.td
    • test/CodeGen/X86/funnel-shift-rot.ll
    • test/CodeGen/X86/rot32.ll
    • test/CodeGen/X86/rot64.ll
  33. Add IR debug info support for Elemental, Pure, and Recursive Procedures.

    Changed by Adrian Prantl - aprantlohnoyoudont@apple.com
    Changed at Thursday, 14-Mar-19 16:29:54 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 331d4e6ff2043153dd6a29e4f53b5c8ed05aca9b

    Comments

    Add IR debug info support for Elemental, Pure, and Recursive Procedures.
    
    Patch by Eric Schweitz!
    
    Differential Revision: https://reviews.llvm.org/D54043
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356163 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • docs/SourceLevelDebugging.rst
    • include/llvm/IR/DebugInfoFlags.def
    • include/llvm/IR/DebugInfoMetadata.h
    • lib/CodeGen/AsmPrinter/DwarfUnit.cpp
    • test/Assembler/disubprogram.ll
  34. [NFC][ARM] Update test

    Changed by Sam Parker - sam.parkerohnoyoudont@arm.com
    Changed at Thursday, 14-Mar-19 15:36:54 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision acbed856d27d6546b7cf69b91220c9b3af58ce50

    Comments

    [NFC][ARM] Update test
    
    Change some regex to handle commutable instructions. 
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356159 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
  35. [x86] prevent infinite looping from vselect commutation (PR41066)

    Changed by Sanjay Patel - spatelohnoyoudont@rotateright.com
    Changed at Thursday, 14-Mar-19 15:32:34 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 9afb620acffec194d77b531b372e8599a8cb1ebd

    Comments

    [x86] prevent infinite looping from vselect commutation (PR41066)
    
    This is an immediate fix for:
    https://bugs.llvm.org/show_bug.cgi?id=41066
    ...but as noted there and the code comments, we should do better
    by stubbing this out sooner.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356158 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/X86/X86ISelLowering.cpp
    • test/CodeGen/X86/avx512-vec-cmp.ll
  36. YAMLIO: Improve template arg deduction for mapOptional

    Changed by Pavel Labath - pavelohnoyoudont@labath.sk
    Changed at Thursday, 14-Mar-19 15:23:40 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision e287d6a791e06558575c29c1ba58123c9c0f49a2

    Comments

    YAMLIO: Improve template arg deduction for mapOptional
    
    Summary:
    The way c++ template argument deduction works, both arguments are used
    to deduce the template type in the three-argument overload of
    mapOptional. This is a problem if the types are slightly different, even
    if they are implicitly convertible. This is fairly easy to trigger with
    integral types, as the default type of most integral constants is int,
    which then requires casting the constant to the type of the other
    argument.
    
    This patch fixes that by using a separate template type for the default
    value, which is then cast to the type of the first argument.  To avoid
    this conversion triggerring conversions marged as explicit, we use
    static_assert to check that the types are implicitly convertible.
    
    Reviewers: zturner, sammccall
    
    Subscribers: kristina, jdoerfert, llvm-commits
    
    Tags: #llvm
    
    Differential Revision: https://reviews.llvm.org/D59142
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356157 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • include/llvm/Support/YAMLTraits.h
    • unittests/Support/YAMLIOTest.cpp
  37. AMDGPU: Scavenge register instead of findUnusedReg

    Changed by Matt Arsenault - Matthew.Arsenaultohnoyoudont@amd.com
    Changed at Thursday, 14-Mar-19 14:19:01 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 9ec5e55104dde136aac5f120cbfb6a1f7546c6b4

    Comments

    AMDGPU: Scavenge register instead of findUnusedReg
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356149 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/AMDGPU/SIRegisterInfo.cpp
  38. GlobalISel: Use multiple returns for intrinsic structs

    Changed by Matt Arsenault - Matthew.Arsenaultohnoyoudont@amd.com
    Changed at Thursday, 14-Mar-19 14:18:56 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision c357f7eb2b610b8d5fb61e9bad52cd70d1797d0d

    Comments

    GlobalISel: Use multiple returns for intrinsic structs
    
    This is consistent with what SelectionDAG does and is much easier to
    work with than the extract sequence with an artificial wide register.
    
    For the AMDGPU control flow intrinsics, this was producing an s128 for
    the i64, i1 tuple return. Any legalization that should apply to a real
    s128 value would badly obscure the direct values that need to be seen.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356147 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
    • lib/CodeGen/GlobalISel/IRTranslator.cpp
    • lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
    • test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
    • test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll
  39. [SampleFDO] add suffix elision control for fcn names

    Changed by Than McIntosh - thanmohnoyoudont@google.com
    Changed at Thursday, 14-Mar-19 13:56:49 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 002b63f0a3bc17dd34d4392f6622b3041d5af32e

    Comments

    [SampleFDO] add suffix elision control for fcn names
    
    Summary:
    Add hooks for determining the policy used to decide whether/how
    to chop off symbol 'suffixes' when locating a given function
    in a sample profile.
    
    Prior to this change, any function symbols of the form "X.Y" were
    elided/truncated into just "X" when looking up things in a sample
    profile data file.
    
    With this change, the policy on suffixes can be changed by adding a
    new attribute "sample-profile-suffix-elision-policy" to the function:
    this attribute can have the value "all" (the default), "selected", or
    "none". A value of "all" preserves the previous behavior (chop off
    everything after the first "." character, then treat that as the
    symbol name). A value of "selected" chops off only the rightmost
    ".llvm.XXXX" suffix (where "XXX" is any string not containing a "."
    char). A value of "none" indicates that names should be left as is.
    
    Subscribers: jdoerfert, wmi, mtrofin, danielcdh, llvm-commits
    
    Tags: #llvm
    
    Differential Revision: https://reviews.llvm.org/D58832
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356146 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • include/llvm/ProfileData/SampleProf.h
    • include/llvm/ProfileData/SampleProfReader.h
    • lib/ProfileData/SampleProfReader.cpp
    • unittests/ProfileData/SampleProfTest.cpp
  40. Note ImmArg in documentation for adding intrinsics

    Changed by Matt Arsenault - Matthew.Arsenaultohnoyoudont@amd.com
    Changed at Thursday, 14-Mar-19 13:46:17 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 32ff027088cf1d734a15cff2273a3d0c79a04d23

    Comments

    Note ImmArg in documentation for adding intrinsics
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356145 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • docs/ExtendingLLVM.rst
  41. ARM: Add ImmArg to intrinsics

    Changed by Matt Arsenault - Matthew.Arsenaultohnoyoudont@amd.com
    Changed at Thursday, 14-Mar-19 13:46:14 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 496c1dd07c49d67874deefd8b19b01fa5da31e12

    Comments

    ARM: Add ImmArg to intrinsics
    
    I found these by asserting in clang for any GCCBuiltin that doesn't
    require mangling and requires a constant for the builtin. This means
    that intrinsics are missing which don't use GCCBuiltin, don't have
    builtins defined in clang, or were missing the constant annotation in
    the builtin definition.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356144 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • include/llvm/IR/IntrinsicsARM.td
    • test/CodeGen/ARM/cdp.ll
    • test/CodeGen/ARM/cdp2.ll
    • test/Verifier/ARM/intrinsic-immarg.ll
    • test/Verifier/ARM/lit.local.cfg
  42. AMDGPU: Don't add unnecessary convergent attributes

    Changed by Matt Arsenault - Matthew.Arsenaultohnoyoudont@amd.com
    Changed at Thursday, 14-Mar-19 13:46:09 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision c06a0f6ec2c5e71efbae73a1d275fb27186408e9

    Comments

    AMDGPU: Don't add unnecessary convergent attributes
    
    These are redundant with the intrinsic declaration.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356143 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
  43. gn build: Merge r356080

    Changed by Hans Wennborg - hansohnoyoudont@hanshq.net
    Changed at Thursday, 14-Mar-19 12:22:50 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision d7620a3317c5b2cd26ecb995c7d9f1e2db95aba7

    Comments

    gn build: Merge r356080
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356139 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • utils/gn/secondary/llvm/lib/BinaryFormat/BUILD.gn
    • utils/gn/secondary/llvm/unittests/BinaryFormat/BUILD.gn
  44. [SystemZ] Remove icmp undef

    Changed by Simon Pilgrim - llvm-devohnoyoudont@redking.me.uk
    Changed at Thursday, 14-Mar-19 11:56:41 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision b85628fbc5c506773345b1387ca9c2e638f91327

    Comments

    [SystemZ] Remove icmp undef 
    
    Prep-work for PR40800 (Add UNDEF handling to SelectionDAG::FoldSetCC)
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356138 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/SystemZ/knownbits.ll
  45. [SystemZ] Regenerate tests to make complete codegen more obvious

    Changed by Simon Pilgrim - llvm-devohnoyoudont@redking.me.uk
    Changed at Thursday, 14-Mar-19 11:54:46 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision c69e0f0517d998aada49e7848f35a29b11a5d678

    Comments

    [SystemZ] Regenerate tests to make complete codegen more obvious
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356137 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/SystemZ/buildvector-00.ll
    • test/CodeGen/SystemZ/dag-combine-03.ll
  46. [llvm-objcopy]Don't implicitly strip sections in segments

    Changed by James Henderson - jh7370ohnoyoudont@my.bristol.ac.uk
    Changed at Thursday, 14-Mar-19 11:47:41 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision d5ba5901b903e6fa04a632131eedf3101c489c81

    Comments

    [llvm-objcopy]Don't implicitly strip sections in segments
    
    This patch changes llvm-objcopy's behaviour to not strip sections that
    are in segments, if they otherwise would be due to a stripping operation
    (--strip-all, --strip-sections, --strip-non-alloc). This preserves the
    segment contents. It does not change the behaviour of --strip-all-gnu
    (although we could choose to do so), because GNU objcopy's behaviour in
    this case seems to be to strip the section, nor does it prevent removing
    of sections in segments with --remove-section (if a user REALLY wants to
    remove a section, we should probably let them, although I could be
    persuaded that warning might be appropriate). Tests have been added to
    show this latter behaviour.
    
    This fixes https://bugs.llvm.org/show_bug.cgi?id=41006.
    
    Reviewed by: grimar, rupprecht, jakehehrlich
    
    Differential Revision: https://reviews.llvm.org/D59293
    
    This is a reland of r356129, attempting to fix greendragon failures
    due to a suspected compatibility issue with od on the greendragon bots
    versus other versions.
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356136 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/tools/llvm-objcopy/ELF/remove-section-in-segment.test
    • test/tools/llvm-objcopy/ELF/strip-all-gnu.test
    • test/tools/llvm-objcopy/ELF/strip-all.test
    • test/tools/llvm-objcopy/ELF/strip-non-alloc.test
    • test/tools/llvm-objcopy/ELF/strip-sections.test
    • tools/llvm-objcopy/ELF/ELFObjcopy.cpp
    • tools/llvm-objcopy/ObjcopyOpts.td
    • tools/llvm-objcopy/StripOpts.td
  47. Fix for buildbots

    Changed by Sam Parker - sam.parkerohnoyoudont@arm.com
    Changed at Thursday, 14-Mar-19 11:38:55 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision b425d6d63ac80ca6f2a5c5942d48ae0f7b9cefd9

    Comments

    Fix for buildbots
    
    Remove unused private field.
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356135 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Transforms/Scalar/LoopStrengthReduce.cpp
  48. Revert r356129 due to greendragon bot failures

    Changed by James Henderson - jh7370ohnoyoudont@my.bristol.ac.uk
    Changed at Thursday, 14-Mar-19 11:23:04 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 2c597b63fe0f0dad93ecf3e8b2a28179e023b94c

    Comments

    Revert r356129 due to greendragon bot failures
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356133 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/tools/llvm-objcopy/ELF/remove-section-in-segment.test
    • test/tools/llvm-objcopy/ELF/strip-all-gnu.test
    • test/tools/llvm-objcopy/ELF/strip-all.test
    • test/tools/llvm-objcopy/ELF/strip-non-alloc.test
    • test/tools/llvm-objcopy/ELF/strip-sections.test
    • tools/llvm-objcopy/ELF/ELFObjcopy.cpp
    • tools/llvm-objcopy/ObjcopyOpts.td
    • tools/llvm-objcopy/StripOpts.td
  49. [ARM][ParallelDSP] Enable multiple uses of loads

    Changed by Sam Parker - sam.parkerohnoyoudont@arm.com
    Changed at Thursday, 14-Mar-19 11:14:13 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 571398105ee6b5aa0927bb55441a1ff8791ca058

    Comments

    [ARM][ParallelDSP] Enable multiple uses of loads
        
    When choosing whether a pair of loads can be combined into a single
    wide load, we check that the load only has a sext user and that sext
    also only has one user. But this can prevent the transformation in
    the cases when parallel macs use the same loaded data multiple times.
        
    To enable this, we need to fix up any other uses after creating the
    wide load: generating a trunc and a shift + trunc pair to recreate
    the narrow values. We also need to keep a record of which loads have
    already been widened.
    
    Differential Revision: https://reviews.llvm.org/D59215
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356132 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/ARM/ARMParallelDSP.cpp
    • test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
    • test/CodeGen/ARM/ParallelDSP/smlad0.ll
    • test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
  50. [NFC][LSR] Cleanup Cost API

    Changed by Sam Parker - sam.parkerohnoyoudont@arm.com
    Changed at Thursday, 14-Mar-19 11:05:07 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 6273747bc3d183848ffc55fafd833200ce22058b

    Comments

    [NFC][LSR] Cleanup Cost API
    
    Create members for Loop, ScalarEvolution, DominatorTree,
    TargetTransformInfo and Formula.
    
    Differential Revision: https://reviews.llvm.org/D58389
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356131 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Transforms/Scalar/LoopStrengthReduce.cpp
  51. [ARM] Run ARMParallelDSP in the IRPasses phase

    Changed by Sam Parker - sam.parkerohnoyoudont@arm.com
    Changed at Thursday, 14-Mar-19 10:57:40 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 01f20a4ee2a218cec7d670a4e5fc04be6cf350aa

    Comments

    [ARM] Run ARMParallelDSP in the IRPasses phase
    
    Run EarlyCSE before ParallelDSP and do this in the backend IR opt
    phase.
    
    Differential Revision: https://reviews.llvm.org/D59257
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356130 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/ARM/ARMTargetMachine.cpp
    • test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll
    • test/CodeGen/ARM/O3-pipeline.ll
    • test/CodeGen/ARM/loop-indexing.ll
    • test/CodeGen/ARM/vldm-sched-a9.ll
    • test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll
    • test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
    • test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll
  52. [llvm-objcopy]Don't implicitly strip sections in segments

    Changed by James Henderson - jh7370ohnoyoudont@my.bristol.ac.uk
    Changed at Thursday, 14-Mar-19 10:20:27 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision e83676d5104ca4d90e404066ea4196a2488451f8

    Comments

    [llvm-objcopy]Don't implicitly strip sections in segments
    
    This patch changes llvm-objcopy's behaviour to not strip sections that
    are in segments, if they otherwise would be due to a stripping operation
    (--strip-all, --strip-sections, --strip-non-alloc). This preserves the
    segment contents. It does not change the behaviour of --strip-all-gnu
    (although we could choose to do so), because GNU objcopy's behaviour in
    this case seems to be to strip the section, nor does it prevent removing
    of sections in segments with --remove-section (if a user REALLY wants to
    remove a section, we should probably let them, although I could be
    persuaded that warning might be appropriate). Tests have been added to
    show this latter behaviour.
    
    This fixes https://bugs.llvm.org/show_bug.cgi?id=41006.
    
    Reviewed by: grimar, rupprecht, jakehehrlich
    
    Differential Revision: https://reviews.llvm.org/D59293
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356129 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/tools/llvm-objcopy/ELF/remove-section-in-segment.test
    • test/tools/llvm-objcopy/ELF/strip-all-gnu.test
    • test/tools/llvm-objcopy/ELF/strip-all.test
    • test/tools/llvm-objcopy/ELF/strip-non-alloc.test
    • test/tools/llvm-objcopy/ELF/strip-sections.test
    • tools/llvm-objcopy/ELF/ELFObjcopy.cpp
    • tools/llvm-objcopy/ObjcopyOpts.td
    • tools/llvm-objcopy/StripOpts.td
  53. gn build: Merge r356082

    Changed by Hans Wennborg - hansohnoyoudont@hanshq.net
    Changed at Thursday, 14-Mar-19 10:10:25 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision f012e914c827754dafe6e542056ab278061ae2e2

    Comments

    gn build: Merge r356082
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356128 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • utils/gn/secondary/llvm/lib/BinaryFormat/BUILD.gn
    • utils/gn/secondary/llvm/unittests/BinaryFormat/BUILD.gn
  54. [RISCV] Fix rL356123

    Changed by Alex Bradbury - asbohnoyoudont@lowrisc.org
    Changed at Thursday, 14-Mar-19 08:31:35 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision ac0d6fee07540817c2e71f4b96280dcc7221be65

    Comments

    [RISCV] Fix rL356123
    
    The wrong version of the patch was committed. This fixes typos that broke the build.
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356124 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/RISCV/RISCVRegisterInfo.cpp
  55. [RISCV][NFC] Rename callee saved regs 'CSR' to CSR_ILP32_LP64 and minor RISCVRegisterInfo refactoring

    Changed by Alex Bradbury - asbohnoyoudont@lowrisc.org
    Changed at Thursday, 14-Mar-19 08:28:48 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision b216751ea8fcedf2ea7db2390ce6cf5862bc0428

    Comments

    [RISCV][NFC] Rename callee saved regs 'CSR' to CSR_ILP32_LP64 and minor RISCVRegisterInfo refactoring
    
    The CSR renaming further prepares the way for an upcoming patch adding support for more
    RISC-V ABIs.
    
    Modify RISCVRegisterInfo::getCalleeSavedRegs and
    RISCVRegisterInfo::getReservedRegs to do MF->getSubtarget<RISCVSubtarget>()
    once rather than multiple times.
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356123 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/RISCV/RISCVCallingConv.td
    • lib/Target/RISCV/RISCVRegisterInfo.cpp
  56. [RISCV] Extend test/CodeGen/RISCV/callee-saved-* to test getCalleePreservedRegs

    Changed by Alex Bradbury - asbohnoyoudont@lowrisc.org
    Changed at Thursday, 14-Mar-19 08:17:44 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 8125ab6f68f9990eec65f4acb743e8ffb7608193

    Comments

    [RISCV] Extend test/CodeGen/RISCV/callee-saved-* to test getCalleePreservedRegs
    
    Add a caller which exhausts regs then calls another function. This allows
    getCalleePreservedRegs to be tested.
    
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356122 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/RISCV/callee-saved-fpr32s.ll
    • test/CodeGen/RISCV/callee-saved-fpr64s.ll
    • test/CodeGen/RISCV/callee-saved-gprs.ll
  57. [X86] Add patterns for rotr by immediate to fix PR41057.

    Changed by Craig Topper - craig.topperohnoyoudont@intel.com
    Changed at Thursday, 14-Mar-19 07:07:26 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 6248ee71f83d81fa8f827f2c74f23e88ff399b9f

    Comments

    [X86] Add patterns for rotr by immediate to fix PR41057.
    
    Prior to the introduction of funnel shift intrinsics we could count on rotate
    by immediates prefering to use rotl since that's what MatchRotate would check
    first. The or+shift pattern doesn't have a direction so one must be chosen
    arbitrarily.
    
    With funnel shift, there is a direction and fshr will try to use rotr first.
    While fshl will try to use rotl first.
    
    This patch adds the isel patterns for rotr to complement the rotl patterns. I've
    put the rotr by 1 patterns in the instruction patterns. And moved the rotl by
    bitwidth-1 patterns to separate Pat patterns.
    
    Fixes PR41057.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356121 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/X86/X86InstrShiftRotate.td
    • test/CodeGen/X86/funnel-shift-rot.ll
    • test/CodeGen/X86/rot32.ll
    • test/CodeGen/X86/rot64.ll
  58. [X86] Add various test cases for PR41057. NFC

    Changed by Craig Topper - craig.topperohnoyoudont@intel.com
    Changed at Thursday, 14-Mar-19 07:07:24 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision b98d8ca15ff81418e0ab5c2ee5310f392f07c3ec

    Comments

    [X86] Add various test cases for PR41057. NFC
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356120 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/X86/funnel-shift-rot.ll
    • test/CodeGen/X86/rot32.ll
    • test/CodeGen/X86/rot64.ll
  59. [GlobalISel][Utils] Add a getConstantVRegVal variant that looks through instrs

    Changed by Quentin Colombet - quentin.colombetohnoyoudont@gmail.com
    Changed at Thursday, 14-Mar-19 01:37:13 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 79ad8c5d8495f4e06c598b17c225ea3a60ecafe3

    Comments

    [GlobalISel][Utils] Add a getConstantVRegVal variant that looks through instrs
    
    getConstantVRegVal used to only look for G_CONSTANT when looking at
    unboxing the value of a vreg. However, constants are sometimes not
    directly used and are hidden behind trunc, s|zext or copy chain of
    computation.
    
    In particular this may be introduced by the legalization process that
    doesn't want to simplify these patterns because it can lead to infine
    loop when legalizing a constant.
    
    To circumvent that problem, add a new variant of getConstantVRegVal,
    named getConstantVRegValWithLookThrough, that allow to look through
    extensions.
    
    Differential Revision: https://reviews.llvm.org/D59227
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356116 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • include/llvm/CodeGen/GlobalISel/Utils.h
    • lib/CodeGen/GlobalISel/InstructionSelector.cpp
    • lib/CodeGen/GlobalISel/Utils.cpp
    • test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll
    • test/CodeGen/X86/GlobalISel/ashr-scalar.ll
    • test/CodeGen/X86/GlobalISel/lshr-scalar.ll
    • test/CodeGen/X86/GlobalISel/shl-scalar.ll
  60. Fixup tests to check for any MCInst number instead of a specific one.

    Changed by Douglas Yung - douglas.yungohnoyoudont@sony.com
    Changed at Thursday, 14-Mar-19 01:24:35 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision c8c4a422420860f7d11d080f0bf5969d2bb4ebbb

    Comments

    Fixup tests to check for any MCInst number instead of a specific one.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356115 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/Mips/llvm-ir/fptosi.ll
    • test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll
  61. [ResetMachineFunctionPass] Add visited functions statistics info

    Changed by Craig Topper - craig.topperohnoyoudont@intel.com
    Changed at Thursday, 14-Mar-19 01:13:15 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 8136aefd779ccd98470aa9ef6ffd5f38aaee9568

    Comments

    [ResetMachineFunctionPass] Add visited functions statistics info
    
    Adding a "NumFunctionsVisited" for collecting the visited function number.
    It can be used to collect function pass rate in some tests,
    the pass rate = (NumberVisited - NumberReset)/NumberVisited.
    e.g. it can be used for caculating GlobalISel pass rate in Test-Suite.
    
    Patch by Tianyang Zhu (zhutianyang)
    
    Differential Revision: https://reviews.llvm.org/D59285
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356114 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/CodeGen/ResetMachineFunctionPass.cpp
  62. [X86] Add 64-bit mode command lines to rot32.ll so that it will demonstrate PR41055 for 32 bit. NFC

    Changed by Craig Topper - craig.topperohnoyoudont@intel.com
    Changed at Thursday, 14-Mar-19 00:23:31 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision f338da057ca605eb43dd5955a36544f3bdbc62b6

    Comments

    [X86] Add 64-bit mode command lines to rot32.ll so that it will demonstrate PR41055 for 32 bit. NFC
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356112 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/X86/rot32.ll
  63. [llvm-objcopy][NFC] Remove unnecessary llvm-objcopy.h #includes

    Changed by Jordan Rupprecht - rupprechtohnoyoudont@google.com
    Changed at Wednesday, 13-Mar-19 23:40:16 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 0502ddb2a607516ef3cbd0fb8a67ca483ceaff81

    Comments

    [llvm-objcopy][NFC] Remove unnecessary llvm-objcopy.h #includes
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356109 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • tools/llvm-objcopy/Buffer.cpp
    • tools/llvm-objcopy/COFF/Reader.cpp
    • tools/llvm-objcopy/COFF/Writer.cpp
    • tools/llvm-objcopy/MachO/MachOObjcopy.cpp
    • tools/llvm-objcopy/MachO/MachOWriter.cpp
  64. [AArch64][GlobalISel] Gardening: Simplify subregister copy in selectBuildVector

    Changed by Jessica Paquette - jpaquetteohnoyoudont@apple.com
    Changed at Wednesday, 13-Mar-19 23:29:54 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 82b9a28c7e3e802d05c86a844804f4d87cf91fce

    Comments

    [AArch64][GlobalISel] Gardening: Simplify subregister copy in selectBuildVector
    
    NFC. Some more preliminary factoring for G_INSERT_VECTOR_ELT.
    
    Also better code-reuse, etc., etc.
    
    Differential Revision: https://reviews.llvm.org/D59323
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356107 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/AArch64/AArch64InstructionSelector.cpp
  65. [GlobalISel][AArch64] Gardening: Factor out vector inserts

    Changed by Jessica Paquette - jpaquetteohnoyoudont@apple.com
    Changed at Wednesday, 13-Mar-19 23:22:23 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 63f4b537b320e626a3c6052a4ce05725671f1152

    Comments

    [GlobalISel][AArch64] Gardening: Factor out vector inserts
    
    Factor out the vector insert code in `selectBuildVector`. Replace part of it
    with `emitScalarToVector`, since it was pretty much equivalent.
    
    This will make implementing G_INSERT_VECTOR_ELT easier.
    
    Differential Revision: https://reviews.llvm.org/D59322
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356106 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/AArch64/AArch64InstructionSelector.cpp
  66. [llvm-objcopy] Cleanup errors from CopyConfig and remove llvm-objcopy.h dependency

    Changed by Jordan Rupprecht - rupprechtohnoyoudont@google.com
    Changed at Wednesday, 13-Mar-19 22:26:01 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 86c9a488021980575711014acfbc04468798ecd6

    Comments

    [llvm-objcopy] Cleanup errors from CopyConfig and remove llvm-objcopy.h dependency
    
    error() was previously cleaned up from CopyConfig, but new uses were introduced.
    
    This also tweaks the error message for --add-symbol to report all invalid flags.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356105 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/tools/llvm-objcopy/ELF/add-symbol.test
    • tools/llvm-objcopy/CopyConfig.cpp
  67. [AIX][CMake] Changes for building on AIX with XL and GCC

    Changed by Jason Liu - jasonliu.developmentohnoyoudont@gmail.com
    Changed at Wednesday, 13-Mar-19 21:50:25 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision b7dc7b58c4c68885238ff360085a8a92fadd93a8

    Comments

    [AIX][CMake] Changes for building on AIX with XL and GCC
    
    Summary:
    In support of IBM's efforts to produce a viable C and C++ LLVM compiler for AIX
    (ref: RFC at http://lists.llvm.org/pipermail/llvm-dev/2019-February/130175.html),
    this patch adds customizations to the CMake files in order to properly
    invoke the host toolchain for the build on AIX.
    Additional changes to enable a successful build will follow.
    
    Patch by Xing Xue
    
    Reviewers: hubert.reinterpretcast, jasonliu, sfertile
    
    Reviewed by: hubert.reinterpretcast
    
    Differential Revision: https://reviews.llvm.org/D58250
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356104 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • cmake/modules/AddLLVM.cmake
    • cmake/modules/HandleLLVMOptions.cmake
    • include/llvm/Config/abi-breaking.h.cmake
  68. [WebAssembly] Improve support for "needed" list in dylink section

    Changed by Sam Clegg - sbcohnoyoudont@chromium.org
    Changed at Wednesday, 13-Mar-19 21:29:20 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 8a89f2de31f740ab9c40c0b33804e16ebb81b90f

    Comments

    [WebAssembly] Improve support for "needed" list in dylink section
    
    This change adds basic support for shared library dependencies
    via the dylink section.
    
    See https://github.com/WebAssembly/tool-conventions/pull/77
    
    Differential Revision: https://reviews.llvm.org/D59237
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356102 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Object/WasmObjectFile.cpp
  69. [GlobalISel][AArch64] Gardening: Factor out code to find lane indices

    Changed by Jessica Paquette - jpaquetteohnoyoudont@apple.com
    Changed at Wednesday, 13-Mar-19 21:19:29 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision d6686b6984bdc4f8111947a4471172036a5aea97

    Comments

    [GlobalISel][AArch64] Gardening: Factor out code to find lane indices
    
    Some more refactoring for G_INSERT_VECTOR_ELT.
    
    Factor out the code used to find a lane index from `selectExtractElt`. Put it
    into a more general-purpose `getConstantValueForReg` function.
    
    This will be shared with the code for G_INSERT_VECTOR_ELT.
    
    Differential Revision: https://reviews.llvm.org/D59324
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356101 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/AArch64/AArch64InstructionSelector.cpp
  70. [AMDGPU] Silence gcc 7 warnings

    Changed by Stanislav Mekhanoshin - Stanislav.Mekhanoshinohnoyoudont@amd.com
    Changed at Wednesday, 13-Mar-19 21:15:52 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision a4638a6a3ae392cbd5100615bc069d88180ab018

    Comments

    [AMDGPU] Silence gcc 7 warnings
    
    Differential Revision: https://reviews.llvm.org/D59330
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356100 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
    • lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    • lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
    • lib/Target/AMDGPU/SIFoldOperands.cpp
    • lib/Target/AMDGPU/SIPeepholeSDWA.cpp
  71. Verifier: Make sure masked load/store alignment is a power of 2

    Changed by Matt Arsenault - Matthew.Arsenaultohnoyoudont@amd.com
    Changed at Wednesday, 13-Mar-19 19:46:34 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 39c8bbd622650d280546377cd5a9283f215925f2

    Comments

    Verifier: Make sure masked load/store alignment is a power of 2
    
    The same should also be done for scatter/gather, but the verifier
    doesn't check those at all now.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356094 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/IR/Verifier.cpp
    • test/Assembler/auto_upgrade_intrinsics.ll
    • test/Transforms/InstCombine/masked_intrinsics.ll
    • test/Verifier/masked-load.ll
    • test/Verifier/masked-store.ll
  72. PowerPC: Add ImmArg to intrinsics

    Changed by Matt Arsenault - Matthew.Arsenaultohnoyoudont@amd.com
    Changed at Wednesday, 13-Mar-19 19:46:34 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 892b8f0cdb48467f6dc370b3940f211aa8d03a20

    Comments

    PowerPC: Add ImmArg to intrinsics
    
    I found these by asserting in clang for any GCCBuiltin that doesn't
    require mangling and requires a constant for the builtin. This means
    that intrinsics are missing which don't use GCCBuiltin, don't have
    builtins defined in clang, or were missing the constant annotation in
    the builtin definition.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356093 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • include/llvm/IR/IntrinsicsPowerPC.td
  73. Hexagon: Add ImmArg to intrinsics

    Changed by Matt Arsenault - Matthew.Arsenaultohnoyoudont@amd.com
    Changed at Wednesday, 13-Mar-19 19:46:33 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 9e46efd856d9091aa507b19f37f5e0c71c4d153c

    Comments

    Hexagon: Add ImmArg to intrinsics
    
    I found these by asserting in clang for any GCCBuiltin that doesn't
    require mangling and requires a constant for the builtin. This means
    that intrinsics are missing which don't use GCCBuiltin, don't have
    builtins defined in clang, or were missing the constant annotation in
    the builtin definition.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356092 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • include/llvm/IR/IntrinsicsHexagon.td
  74. SystemZ: Add ImmArg to intrinsics

    Changed by Matt Arsenault - Matthew.Arsenaultohnoyoudont@amd.com
    Changed at Wednesday, 13-Mar-19 19:46:32 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision bb7e40de731597a9fc67705cfd4e27204da94311

    Comments

    SystemZ: Add ImmArg to intrinsics
    
    I found these by asserting in clang for any GCCBuiltin that doesn't
    require mangling and requires a constant for the builtin. This means
    that intrinsics are missing which don't use GCCBuiltin, don't have
    builtins defined in clang, or were missing the constant annotation in
    the builtin definition.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356091 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • include/llvm/IR/IntrinsicsSystemZ.td
    • test/Verifier/SystemZ/intrinsic-immarg.ll
    • test/Verifier/SystemZ/lit.local.cfg
  75. Mips: Add ImmArg to intrinsics

    Changed by Matt Arsenault - Matthew.Arsenaultohnoyoudont@amd.com
    Changed at Wednesday, 13-Mar-19 19:07:59 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision f3a3d439652b45b3e38e15ba785105c38da480dd

    Comments

    Mips: Add ImmArg to intrinsics
    
    I found these by asserting in clang for any GCCBuiltin that doesn't
    require mangling and requires a constant for the builtin. This means
    that intrinsics are missing which don't use GCCBuiltin, don't have
    builtins defined in clang, or were missing the constant annotation in
    the builtin definition.
    
    I'm not sure what's going on with the immediates.ll test. It seems to
    be intended to test invalid cases like this, but then tries to handle
    some of them anyway. I've moved the cases that were inconsistent with
    the GCCBuiltin definition so they don't test the codegen anymore.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356085 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • include/llvm/IR/IntrinsicsMips.td
    • test/CodeGen/Mips/msa/immediates.ll
    • test/Verifier/Mips/intrinsic-immarg.ll
    • test/Verifier/Mips/lit.local.cfg
  76. [X86] Remove icmp undef in more reduced tests

    Changed by Simon Pilgrim - llvm-devohnoyoudont@redking.me.uk
    Changed at Wednesday, 13-Mar-19 19:07:54 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 4aa20a4a6d28ea20124bc7658994640f6e5af7ee

    Comments

    [X86] Remove icmp undef in more reduced tests
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356084 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/X86/block-placement.ll
    • test/CodeGen/X86/sext-i1.ll
  77. [X86] Regenerate tail call tests

    Changed by Simon Pilgrim - llvm-devohnoyoudont@redking.me.uk
    Changed at Wednesday, 13-Mar-19 19:04:45 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision dca8e63deaa4abfc879cd40a963a8366715ad70c

    Comments

    [X86] Regenerate tail call tests
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356083 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/X86/tail-dup-merge-loop-headers.ll
    • test/CodeGen/X86/tail-dup-repeat.ll
  78. [MsgPack] Removed MsgPackTypes

    Changed by Tim Renouf - tpr.llvmohnoyoudont@botech.co.uk
    Changed at Wednesday, 13-Mar-19 18:56:33 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 74fba6521c19a5ef8676d999fcc8efd17f77e748

    Comments

    [MsgPack] Removed MsgPackTypes
    
    Summary:
    MsgPackTypes has been replaced by the lighter-weight MsgPackDocument.
    
    Differential Revision: https://reviews.llvm.org/D57025
    
    Change-Id: Ia7069880ef29f55490abbe5d8ae15f25cc1490a4
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356082 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • include/llvm/BinaryFormat/MsgPackTypes.h
    • lib/BinaryFormat/CMakeLists.txt
    • lib/BinaryFormat/MsgPackTypes.cpp
    • unittests/BinaryFormat/CMakeLists.txt
    • unittests/BinaryFormat/MsgPackTypesTest.cpp
  79. [AMDGPU] Switched HSA metadata to use MsgPackDocument

    Changed by Tim Renouf - tpr.llvmohnoyoudont@botech.co.uk
    Changed at Wednesday, 13-Mar-19 18:55:50 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 6cce665f8058bc42b2531c3e7bf6712ecbe4d7af

    Comments

    [AMDGPU] Switched HSA metadata to use MsgPackDocument
    
    Summary:
    MsgPackDocument is the lighter-weight replacement for MsgPackTypes. This
    commit switches AMDGPU HSA metadata processing to use MsgPackDocument
    instead of MsgPackTypes.
    
    Differential Revision: https://reviews.llvm.org/D57024
    
    Change-Id: I0751668013abe8c87db01db1170831a76079b3a6
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356081 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • include/llvm/BinaryFormat/AMDGPUMetadataVerifier.h
    • lib/BinaryFormat/AMDGPUMetadataVerifier.cpp
    • lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
    • lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h
    • lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
    • lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
    • test/CodeGen/AMDGPU/hsa-metadata-deduce-ro-arg-v3.ll
    • test/CodeGen/AMDGPU/hsa-metadata-enqueu-kernel-v3.ll
    • test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full-v3.ll
    • test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v3.ll
    • test/CodeGen/AMDGPU/hsa-metadata-images-v3.ll
    • test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props-v3.ll
    • test/MC/AMDGPU/hsa-metadata-kernel-args-v3.s
    • test/MC/AMDGPU/hsa-metadata-kernel-attrs-v3.s
    • test/MC/AMDGPU/hsa-metadata-kernel-code-props-v3.s
    • test/MC/AMDGPU/hsa-v3.s
    • tools/llvm-readobj/ELFDumper.cpp
  80. [MsgPack] New MsgPackDocument class

    Changed by Tim Renouf - tpr.llvmohnoyoudont@botech.co.uk
    Changed at Wednesday, 13-Mar-19 18:54:47 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 3589fdddf4b9cce83883a55a3f77ddee30d6a6e6

    Comments

    [MsgPack] New MsgPackDocument class
    
    Summary:
    A class that exposes a simple in-memory representation of a document of
    MsgPack objects, that can be read from and written to MsgPack, read from
    and written to YAML, and inspected and modified in memory. This is
    intended to be a lighter-weight (in terms of memory allocations)
    replacement for MsgPackTypes.
    
    Two subsequent changes will:
    1. switch AMDGPU HSA metadata to using MsgPackDocument instead of
       MsgPackTypes;
    2. add MsgPack AMDGPU PAL metadata via MsgPackDocument.
    
    Differential Revision: https://reviews.llvm.org/D57023
    
    Change-Id: Ie15a054831d5a6467c5867c064c8f8f6b80270e1
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356080 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • include/llvm/BinaryFormat/MsgPackDocument.h
    • lib/BinaryFormat/CMakeLists.txt
    • lib/BinaryFormat/MsgPackDocument.cpp
    • lib/BinaryFormat/MsgPackDocumentYAML.cpp
    • unittests/BinaryFormat/CMakeLists.txt
    • unittests/BinaryFormat/MsgPackDocumentTest.cpp
  81. [X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b()

    Changed by Craig Topper - craig.topperohnoyoudont@intel.com
    Changed at Wednesday, 13-Mar-19 18:48:50 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 5db1718aa6e6ea1cc4964ab1162a91f6429e3d75

    Comments

    [X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b()
    
    The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well.
    
    We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass.
    
    I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue.
    
    Differential Revision: https://reviews.llvm.org/D59308
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356078 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/X86/X86ISelLowering.cpp
    • lib/Target/X86/X86InstrInfo.td
    • lib/Target/X86/X86Subtarget.h
    • test/CodeGen/X86/atomic128.ll
    • test/CodeGen/X86/atomicf128.ll
  82. [X86] Avoid icmp undef in reduced tests

    Changed by Simon Pilgrim - llvm-devohnoyoudont@redking.me.uk
    Changed at Wednesday, 13-Mar-19 18:36:59 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision ad03152cf75950313d3756463611917d04e84450

    Comments

    [X86] Avoid icmp undef in reduced tests
    
    Because we don't currently simplify icmp with undef in DAG, bugpoint loves to introduce them during reduction.
    
    This is a small step towards re-adding non-undef values into some of the simpler tests so that they should still test correctly and emit similar/same codegen.
    
    Prep work for PR40800 ([SelectionDAG] Add UNDEF handling to SelectionDAG::FoldSetCC).
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356076 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/X86/2010-02-23-DAGCombineBug.ll
    • test/CodeGen/X86/combine-pmuldq.ll
    • test/CodeGen/X86/copy-eflags.ll
    • test/CodeGen/X86/machine-trace-metrics-crash.ll
    • test/CodeGen/X86/pr22338.ll
    • test/CodeGen/X86/pr31271.ll
    • test/CodeGen/X86/pr32588.ll
    • test/CodeGen/X86/pr32610.ll
    • test/CodeGen/X86/pr33828.ll
    • test/CodeGen/X86/pr38539.ll
    • test/CodeGen/X86/pr38743.ll
    • test/CodeGen/X86/sext-i1.ll
    • test/CodeGen/X86/trunc-store.ll
  83. [RISCV] Regenerate test/CodeGen/RISCV/legalize-fneg.ll after rL356068

    Changed by Alex Bradbury - asbohnoyoudont@lowrisc.org
    Changed at Wednesday, 13-Mar-19 18:25:23 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 83f786b4bac3c06ee02651bf31c59ddbb8ed32d4

    Comments

    [RISCV] Regenerate test/CodeGen/RISCV/legalize-fneg.ll after rL356068
    
    rL356068 caused some minor re-orderings. Regenerate legalize-fneg.ll to
    reflect this, and remove the NOLIB check lines (they're redundant given that
    the RV32I and RV64I check lines generated by update_llc_test_checks.py already
    demonstrate there is no libcall).
    
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356074 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/RISCV/legalize-fneg.ll
  84. Regenerate test

    Changed by Simon Pilgrim - llvm-devohnoyoudont@redking.me.uk
    Changed at Wednesday, 13-Mar-19 18:18:24 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 1c13a5b043852cb6d4084ea01075c896f19d10af

    Comments

    Regenerate test
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356071 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/X86/2010-02-23-DAGCombineBug.ll
  85. [DAGCombiner] Fix Comment. NFC.

    Changed by Nirav Dave - niravdohnoyoudont@google.com
    Changed at Wednesday, 13-Mar-19 17:44:40 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision e79d0df477b61d2f6b17d0514dda57ff59293922

    Comments

    [DAGCombiner] Fix Comment. NFC.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356069 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  86. [DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.

    Changed by Nirav Dave - niravdohnoyoudont@google.com
    Changed at Wednesday, 13-Mar-19 17:07:09 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 154874adc5349d2c70926e53d5fcb7e82b0a661b

    Comments

    [DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
    
    Summary:
    A number of optimizations are inhibited by single-use TokenFactors not
    being merged into the TokenFactor using it. This makes we consider if
    we can do the merge immediately.
    
    Most tests changes here are due to the change in visitation causing
    minor reorderings and associated reassociation of paired memory
    operations.
    
    CodeGen tests with non-reordering changes:
    
      X86/aligned-variadic.ll -- memory-based add folded into stored leaq
      value.
    
      X86/constant-combiners.ll -- Optimizes out overlap between stores.
    
      X86/pr40631_deadstore_elision -- folds constant byte store into
      preceding quad word constant store.
    
    Reviewers: RKSimon, craig.topper, spatel, efriedma, courbet
    
    Reviewed By: courbet
    
    Subscribers: dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, eraman, hiraditya, kbarton, jrtc27, atanasyan, jsji, llvm-commits
    
    Tags: #llvm
    
    Differential Revision: https://reviews.llvm.org/D59260
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356068 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    • test/CodeGen/AArch64/aarch64_win64cc_vararg.ll
    • test/CodeGen/AArch64/addr-of-ret-addr.ll
    • test/CodeGen/AArch64/alloca.ll
    • test/CodeGen/AArch64/arm64-memcpy-inline.ll
    • test/CodeGen/AArch64/arm64-variadic-aapcs.ll
    • test/CodeGen/AArch64/win64_vararg.ll
    • test/CodeGen/AMDGPU/call-argument-types.ll
    • test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
    • test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll
    • test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll
    • test/CodeGen/ARM/memset-inline.ll
    • test/CodeGen/ARM/thumb1_return_sequence.ll
    • test/CodeGen/ARM/unaligned_load_store.ll
    • test/CodeGen/AVR/calling-conv/c/basic.ll
    • test/CodeGen/AVR/directmem.ll
    • test/CodeGen/BPF/undef.ll
    • test/CodeGen/MSP430/cc_args.ll
    • test/CodeGen/Mips/v2i16tof32.ll
    • test/CodeGen/PowerPC/f128-aggregates.ll
    • test/CodeGen/PowerPC/ppc64-byval-align.ll
    • test/CodeGen/Thumb/frame-access.ll
    • test/CodeGen/Thumb/mvn.ll
    • test/CodeGen/X86/aligned-variadic.ll
    • test/CodeGen/X86/atomic-idempotent.ll
    • test/CodeGen/X86/avx-load-store.ll
    • test/CodeGen/X86/btc_bts_btr.ll
    • test/CodeGen/X86/combine-sbb.ll
    • test/CodeGen/X86/constant-combines.ll
    • test/CodeGen/X86/min-legal-vector-width.ll
    • test/CodeGen/X86/musttail-varargs.ll
    • test/CodeGen/X86/musttail.ll
    • test/CodeGen/X86/nosse-vector.ll
    • test/CodeGen/X86/oddshuffles.ll
    • test/CodeGen/X86/pr40631_deadstore_elision.ll
    • test/CodeGen/X86/rotate.ll
    • test/CodeGen/X86/rotate4.ll
    • test/CodeGen/X86/sadd_sat_vec.ll
    • test/CodeGen/X86/shift-and.ll
    • test/CodeGen/X86/shrink_vmul-widen.ll
    • test/CodeGen/X86/shrink_vmul.ll
    • test/CodeGen/X86/ssub_sat_vec.ll
    • test/CodeGen/X86/uadd_sat_vec.ll
    • test/CodeGen/X86/usub_sat_vec.ll
    • test/CodeGen/X86/vastart-defs-eflags.ll
    • test/CodeGen/X86/vec_fpext.ll
    • test/CodeGen/X86/widen_cast-2.ll
    • test/CodeGen/X86/widen_load-2.ll
    • test/CodeGen/X86/win64_frame.ll
    • test/CodeGen/X86/win64_vararg.ll
    • test/CodeGen/X86/x86-64-ms_abi-vararg.ll
    • test/CodeGen/XCore/byVal.ll
  87. [X86][AVX] Add X86ISD::VTRUNC handling to SimplifyDemandedVectorEltsForTargetNode

    Changed by Simon Pilgrim - llvm-devohnoyoudont@redking.me.uk
    Changed at Wednesday, 13-Mar-19 17:00:18 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision e3707b846d4b72f4199b35e43b6e1d543f7f93ae

    Comments

    [X86][AVX] Add X86ISD::VTRUNC handling to SimplifyDemandedVectorEltsForTargetNode
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356067 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/X86/X86ISelLowering.cpp
    • test/CodeGen/X86/shuffle-vs-trunc-256-widen.ll
  88. [X86][AVX] Add combineConcatVectors support to improve subvector handling

    Changed by Simon Pilgrim - llvm-devohnoyoudont@redking.me.uk
    Changed at Wednesday, 13-Mar-19 16:37:30 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 17d355768ce4c65c78260b3d3f1b54cb085e7ae2

    Comments

    [X86][AVX] Add combineConcatVectors support to improve subvector handling
    
    Attempt to combine CONCAT_VECTORS nodes, which we only really have pre-legalization.
    
    This encourages a lot of X86ISD::SUBV_BROADCAST generation, so I've added SimplifyDemandedVectorEltsForTargetNode handling for this at the same time.
    
    The X86ISD::VTRUNC regression in shuffle-vs-trunc-256-widen.ll will be handled in a future commit.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356064 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/X86/X86ISelLowering.cpp
    • test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
    • test/CodeGen/X86/oddshuffles.ll
    • test/CodeGen/X86/pr34657.ll
    • test/CodeGen/X86/shuffle-vs-trunc-256-widen.ll
    • test/CodeGen/X86/subvector-broadcast.ll
  89. [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer

    Changed by Alex Bradbury - asbohnoyoudont@lowrisc.org
    Changed at Wednesday, 13-Mar-19 16:33:45 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision ed761d68673372e6405a73e08e375ac0219fad82

    Comments

    [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
    
    This follows similar logic in the ARM and Mips backends, and allows the free
    use of s0 in functions without a dedicated frame pointer. The changes in
    callee-saved-gprs.ll most clearly show the effect of this patch.
    
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356063 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/RISCV/RISCVRegisterInfo.cpp
    • test/CodeGen/RISCV/atomic-rmw.ll
    • test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
    • test/CodeGen/RISCV/callee-saved-gprs.ll
    • test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
    • test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
    • test/CodeGen/RISCV/calling-conv-ilp32.ll
    • test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
    • test/CodeGen/RISCV/calling-conv-lp64.ll
    • test/CodeGen/RISCV/calls.ll
    • test/CodeGen/RISCV/double-intrinsics.ll
    • test/CodeGen/RISCV/double-mem.ll
    • test/CodeGen/RISCV/float-br-fcmp.ll
    • test/CodeGen/RISCV/float-intrinsics.ll
    • test/CodeGen/RISCV/float-mem.ll
    • test/CodeGen/RISCV/large-stack.ll
    • test/CodeGen/RISCV/remat.ll
    • test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
    • test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
    • test/CodeGen/RISCV/vararg.ll
  90. [RISCV] Add tests for callee-saved GPRs, FPR32s, and FPR64s

    Changed by Alex Bradbury - asbohnoyoudont@lowrisc.org
    Changed at Wednesday, 13-Mar-19 16:14:16 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 752b9de47d1eacab1c208cfddd3fa7631ec66845

    Comments

    [RISCV] Add tests for callee-saved GPRs, FPR32s, and FPR64s
    
    Note that s0 need not be marked reserved if the frame pointer isn't used. For
    the ILP32 and LP64 soft float ABIS that are currently support, all FPRs are
    always considered temporaries.
    
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356061 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/RISCV/callee-saved-fpr32s.ll
    • test/CodeGen/RISCV/callee-saved-fpr64s.ll
    • test/CodeGen/RISCV/callee-saved-gprs.ll
  91. [mips] Join some adjacent `let DecoderNamespace` blocks. NFC

    Changed by Simon Atanasyan - simonohnoyoudont@atanasyan.com
    Changed at Wednesday, 13-Mar-19 16:00:42 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 47dc3c1743853158dde785b6837bda115ae433c5

    Comments

    [mips] Join some adjacent `let DecoderNamespace` blocks. NFC
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356059 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/Mips/MicroMipsInstrInfo.td
  92. [NFC][CMake] Improve Status message in the iOS toolchain file

    Changed by Louis Dionne - ldionneohnoyoudont@apple.com
    Changed at Wednesday, 13-Mar-19 15:35:21 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 439680dbe5bb29fe5777213bede58e9c821fb296

    Comments

    [NFC][CMake] Improve Status message in the iOS toolchain file
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356056 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • cmake/platforms/iOS.cmake
  93. [AArch64] Add test/CodeGen/AArch64/vecreduce-fadd.ll

    Changed by Sander de Smalen - sander.desmalenohnoyoudont@arm.com
    Changed at Wednesday, 13-Mar-19 15:18:27 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision c409047310b3f2aca145bab940982fd537b867f8

    Comments

    [AArch64] Add test/CodeGen/AArch64/vecreduce-fadd.ll
    
    This test is added to see difference created by:
    
      https://reviews.llvm.org/D59259
    
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356054 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/AArch64/vecreduce-fadd.ll
  94. [x86] limit extractelement of setcc to pre-legalization

    Changed by Sanjay Patel - spatelohnoyoudont@rotateright.com
    Changed at Wednesday, 13-Mar-19 14:49:52 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision b1c30dbc6329056d2c6b9693f6902d9c445bb77a

    Comments

    [x86] limit extractelement of setcc to pre-legalization
    
    A fuzzer found the crasher:
    https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=13700
    
    The bug was introduced recently here:
    rL355741
    
    This is the quick fix. If we need to do this transform
    later, then we'd have to extend/truncate the vector setcc
    element type to the scalar setcc type (i8). 
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356053 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/X86/X86ISelLowering.cpp
    • test/CodeGen/X86/extractelement-fp.ll
  95. [mips] Fix encoding of the `mov.d` command for microMIPS R6

    Changed by Simon Atanasyan - simonohnoyoudont@atanasyan.com
    Changed at Wednesday, 13-Mar-19 14:23:12 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision a63c4ac08c2e5b52ed9f4fdf43c3be709496fb19

    Comments

    [mips] Fix encoding of the `mov.d` command for microMIPS R6
    
    Before this change LLVM emits non-microMIPS variant of the `mov.d`
    command for microMIPS code.
    
    Differential Revision: http://reviews.llvm.org/D59045
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356052 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/Mips/MicroMips32r6InstrInfo.td
    • lib/Target/Mips/MicroMipsInstrFPU.td
    • lib/Target/Mips/MipsInstrFPU.td
    • test/CodeGen/Mips/llvm-ir/fptosi.ll
    • test/CodeGen/Mips/micromips-mtc-mfc.ll
    • test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll
  96. [mips] Define `mov.d` instructions using `ABSS_M` multiclass. NFC

    Changed by Simon Atanasyan - simonohnoyoudont@atanasyan.com
    Changed at Wednesday, 13-Mar-19 14:22:58 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 59c736bd3e6335ec8ddeecd9127f2453edc9e1c2

    Comments

    [mips] Define `mov.d` instructions using `ABSS_M` multiclass. NFC
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356051 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/Mips/MipsInstrFPU.td
  97. Re-land r354244 "[DAGCombiner] Eliminate dead stores to stack."

    Changed by Clement Courbet - courbetohnoyoudont@google.com
    Changed at Wednesday, 13-Mar-19 13:56:23 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision e963c6818dd6c48771e68dc2bcf42bd82ad9f1a1

    Comments

    Re-land r354244 "[DAGCombiner] Eliminate dead stores to stack."
    
    Always check candidates for hasOtherUses(), not only stores.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356050 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    • test/CodeGen/X86/swap.ll
    • test/DebugInfo/COFF/lexicalblock.ll
  98. Fix signed/unsigned mismatch warning. NFCI.

    Changed by Simon Pilgrim - llvm-devohnoyoudont@redking.me.uk
    Changed at Wednesday, 13-Mar-19 13:14:14 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 17d2bf7db1534b932c18866cea440693cf1404ff

    Comments

    Fix signed/unsigned mismatch warning. NFCI.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356046 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/X86/X86ISelLowering.cpp
  99. [mips] Map SW instruction to its microMIPS R6 variant

    Changed by Simon Atanasyan - simonohnoyoudont@atanasyan.com
    Changed at Wednesday, 13-Mar-19 13:09:30 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision e853018a81d2c6fc41347a7daad37036bf0b9889

    Comments

    [mips] Map SW instruction to its microMIPS R6 variant
    
    To provide mapping between standard and microMIPS R6 variants of the
    `sw` command we have to rename SWSP_xxx commands from "sw" to "swsp".
    Otherwise `tablegen` starts to show the error `Multiple matches found
    for `SW'`. After that to restore printing SWSP command as `sw`, I add
    an appropriate `MipsInstAlias` instance.
    
    We also need to implement "size reduction" for microMIPS R6. But this
    task is for separate patch. After that the `micromips-lwsp-swsp.ll` test
    case will be extended.
    
    Differential Revision: http://reviews.llvm.org/D59046
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356045 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/Mips/MicroMips32r6InstrInfo.td
    • lib/Target/Mips/MicroMipsInstrInfo.td
    • lib/Target/Mips/MipsInstrInfo.td
    • test/CodeGen/Mips/micromips-sw.ll
    • test/MC/Mips/macro-ld-sd.s
  100. [RISCV] Regenerate umulo-128-legalisation-lowering.ll

    Changed by Alex Bradbury - asbohnoyoudont@lowrisc.org
    Changed at Wednesday, 13-Mar-19 12:33:44 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 9f9dd8f5478c6f52032b6fcd82cd1b19353bb8bb

    Comments

    [RISCV] Regenerate umulo-128-legalisation-lowering.ll
    
    Upstream changes have improved codegen, reducing stack usage. Regenerate the test.
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356044 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
  101. <blame list capped at 100 commits>

    Changed by <blame list capped at 100 commits> -
    Changed at N/A
    Repository
    Branch
    Revision

    Comments

    <blame list capped at 100 commits>
  102. Failed to fetch blame information

    Changed by
    Changed at N/A
    Repository
    Branch

    Comments

    Failed to fetch blame information
    unable to find previous build