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Builder linux Build 4017 Canonical Ubuntu

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Revision d8706fcd747d2129b2c00045dd8d8191b115f26a

Infra

Steps and Logs

Show:
  1. ( 7 ms ) setup_build

    running recipe: “wasm_llvm”

  2. ( 4 secs ) bot_update

    [21GB/290GB used (7%)]

  3. ( 2 hrs 3 mins ) annotated steps
  4. ( 1 mins 23 secs ) Clobbering work dir
  5. ( 29 mins 11 secs ) Sync Repos
  6. ( 4 mins 18 secs ) LLVM
  7. ( 18 mins 24 secs ) LLVM regression tests
  8. ( 1 mins 7 secs ) V8
  9. ( 12 secs ) jsvu
  10. ( 11 secs ) WABT
  11. ( 11 secs ) binaryen
  12. ( 1 mins 41 secs ) fastcomp
  13. ( 8 secs ) emscripten
  14. ( 2 mins 20 secs ) emscripten (asm2wasm)
  15. ( 1 mins 20 secs ) emscripten (emwasm)
  16. ( 10 secs ) musl
  17. ( 1 secs ) compiler-rt
  18. ( 15 secs ) libcxx
  19. ( 13 secs ) libcxxabi
  20. ( 1 mins 53 secs ) Archive binaries
  21. ( 7 mins 46 secs ) Debian package
  22. ( 16 secs ) Compile LLVM Torture (O0)
  23. ( 2 secs ) Execute LLVM Torture (validate, O0)
  24. ( 19 secs ) Compile LLVM Torture (O2)
  25. ( 2 secs ) Execute LLVM Torture (validate, O2)
  26. ( 13 secs ) Link LLVM Torture (lld, O0)
  27. ( 13 secs ) Link LLVM Torture (lld, O2)
  28. ( 12 secs ) Execute LLVM Torture (d8, O0)
  29. ( 11 secs ) Execute LLVM Torture (d8, O2)
  30. ( 4 mins 15 secs ) Compile LLVM Torture (asm2wasm, O0)
  31. ( 8 mins 43 secs ) Compile LLVM Torture (asm2wasm, O3)
  32. ( 12 secs ) Execute LLVM Torture (asm2wasm, O0)
  33. ( 5 secs ) Execute LLVM Torture (asm2wasm, O3)
  34. ( 2 mins 47 secs ) Compile LLVM Torture (emwasm, O0)
  35. ( 7 mins 35 secs ) Compile LLVM Torture (emwasm, O3)
  36. ( 9 secs ) Execute LLVM Torture (emwasm, O0)
  37. ( 5 secs ) Execute LLVM Torture (emwasm, O3)
  38. ( 16 mins 3 secs ) Execute emscripten testsuite (emwasm)
  39. ( 11 mins 7 secs ) Execute emscripten testsuite (asm2wasm)
  40. ( 1 secs ) Execute emscripten wasm simd
  41. ( 17 secs ) Summary
  42. ( 0 ) recipe result

Timing

Create Thursday, 14-Mar-19 22:54:17 UTC
Start Thursday, 14-Mar-19 22:54:21 UTC
End Friday, 15-Mar-19 00:58:45 UTC
Pending 3 secs
Execution 2 hrs 4 mins

Tags

KeyValue
buildset commit/git/d8706fcd747d2129b2c00045dd8d8191b115f26a
buildset commit/gitiles/llvm.googlesource.com/llvm/+/d8706fcd747d2129b2c00045dd8d8191b115f26a
scheduler_invocation_id 9084400425309540688
scheduler_job_id wasm/linux
user_agent luci-scheduler

Input Properties

NameValue
$recipe_engine/runtime { "is_experimental": false, "is_luci": true }
branch "refs/heads/master"
buildername "linux"
buildnumber 4017
mastername "client.wasm.llvm"
repository "https://llvm.googlesource.com/llvm"
revision "d8706fcd747d2129b2c00045dd8d8191b115f26a"

Output Properties

NameValue
$recipe_engine/path { "cache_dir": "/b/swarming/w/ir/cache", "temp_dir": "/b/swarming/w/ir/tmp/rt" }
$recipe_engine/runtime { "is_experimental": false, "is_luci": true }
bot_id "swarm2469-c4"
branch "refs/heads/master"
buildername "linux"
buildnumber 4017
got_revision "26b4a64918d418dbe64a2bee01d94fa7eaebb80c"
got_waterfall_revision "5fd6d5d2b27876f331efbda4b9ca5fc6294185ef"
mastername "client.wasm.llvm"
path_config "generic"
recipe "wasm_llvm"
repository "https://llvm.googlesource.com/llvm"
revision "d8706fcd747d2129b2c00045dd8d8191b115f26a"

All Changes

  1. MIR: Allow targets to serialize MachineFunctionInfo

    Changed by Matt Arsenault - Matthew.Arsenaultohnoyoudont@amd.com
    Changed at Thursday, 14-Mar-19 22:54:43 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision d8706fcd747d2129b2c00045dd8d8191b115f26a

    Comments

    MIR: Allow targets to serialize MachineFunctionInfo
    
    This has been a very painful missing feature that has made producing
    reduced testcases difficult. In particular the various registers
    determined for stack access during function lowering were necessary to
    avoid undefined register errors in a large percentage of
    cases. Implement a subset of the important fields that need to be
    preserved for AMDGPU.
    
    Most of the changes are to support targets parsing register fields and
    properly reporting errors. The biggest sort-of bug remaining is for
    fields that can be initialized from the IR section will be overwritten
    by a default initialized machineFunctionInfo section. Another
    remaining bug is the machineFunctionInfo section is still printed even
    if empty.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356215 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • include/llvm/CodeGen/MIRParser/MIParser.h
    • include/llvm/CodeGen/MIRYamlMapping.h
    • include/llvm/CodeGen/MachineModuleInfo.h
    • include/llvm/Target/TargetMachine.h
    • lib/CodeGen/MIRParser/MIParser.cpp
    • lib/CodeGen/MIRParser/MIRParser.cpp
    • lib/CodeGen/MIRPrinter.cpp
    • lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    • lib/Target/AMDGPU/AMDGPUTargetMachine.h
    • lib/Target/AMDGPU/LLVMBuild.txt
    • lib/Target/AMDGPU/SIISelLowering.cpp
    • lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
    • lib/Target/AMDGPU/SIMachineFunctionInfo.h
    • test/CodeGen/AMDGPU/scalar-store-cache-flush.mir
    • test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
    • test/CodeGen/AMDGPU/spill-before-exec.mir
    • test/CodeGen/AMDGPU/spill-empty-live-interval.mir
    • test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
    • test/CodeGen/AMDGPU/subreg-split-live-in-error.mir
    • test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
    • test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
    • test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
    • test/CodeGen/MIR/AMDGPU/machine-function-info.ll
    • test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
    • test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
    • test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
    • test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir
    • test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
    • test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
    • test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir
    • test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir
  2. [AArch64][GlobalISel] Add isel support for G_UADDO on s32s and s64s

    Changed by Jessica Paquette - jpaquetteohnoyoudont@apple.com
    Changed at Thursday, 14-Mar-19 22:54:29 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 4a50374b480f6aa06cf8175b694395937eaad82f

    Comments

    [AArch64][GlobalISel] Add isel support for G_UADDO on s32s and s64s
    
    This adds instruction selection support for G_UADDO on s32s and s64s.
    
    Also
    - Add an instruction selection test
    - Update the arm64-xaluo.ll test to show that we generate the correct assembly
    
    Differential Revision: https://reviews.llvm.org/D58734
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356214 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/AArch64/AArch64InstructionSelector.cpp
    • lib/Target/AArch64/AArch64LegalizerInfo.cpp
    • test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    • test/CodeGen/AArch64/GlobalISel/select-uaddo.mir
    • test/CodeGen/AArch64/arm64-xaluo.ll