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Builder linux Build 4011 Canonical Ubuntu

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Failure
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Failure Sync Repos

Input

Revision 48dc9cf87f3a93015ecccad29fcf36d22923a984

Infra

Steps and Logs

Show:
  1. ( 6 ms ) setup_build

    running recipe: “wasm_llvm”

  2. ( 3 secs ) bot_update

    [21GB/290GB used (7%)]

  3. ( 24 secs ) annotated steps
  4. ( 34 secs ) Sync Repos
  5. ( 0 ) Failure reason

Timing

Create Thursday, 14-Mar-19 20:51:17 UTC
Start Thursday, 14-Mar-19 20:51:44 UTC
End Thursday, 14-Mar-19 20:52:39 UTC
Pending 26 secs
Execution 55 secs

Tags

KeyValue
buildset commit/git/48dc9cf87f3a93015ecccad29fcf36d22923a984
buildset commit/gitiles/llvm.googlesource.com/llvm/+/48dc9cf87f3a93015ecccad29fcf36d22923a984
scheduler_invocation_id 9084408163964989072
scheduler_job_id wasm/linux
user_agent luci-scheduler

Input Properties

NameValue
$recipe_engine/runtime { "is_experimental": false, "is_luci": true }
branch "refs/heads/master"
buildername "linux"
buildnumber 4011
mastername "client.wasm.llvm"
repository "https://llvm.googlesource.com/llvm"
revision "48dc9cf87f3a93015ecccad29fcf36d22923a984"

Output Properties

NameValue
$recipe_engine/path { "cache_dir": "/b/swarming/w/ir/cache", "temp_dir": "/b/swarming/w/ir/tmp/rt" }
$recipe_engine/runtime { "is_experimental": false, "is_luci": true }
bot_id "swarm2469-c4"
branch "refs/heads/master"
buildername "linux"
buildnumber 4011
got_revision "11f160de8d6d9baccf9b0479346f2163486620e5"
got_waterfall_revision "b0d7ba40c108aa169f37e023454e828dc737a0ed"
mastername "client.wasm.llvm"
path_config "generic"
recipe "wasm_llvm"
repository "https://llvm.googlesource.com/llvm"
revision "48dc9cf87f3a93015ecccad29fcf36d22923a984"

All Changes

  1. [ARC] Add more load/store variants.

    Changed by Pete Couperus - petecoupohnoyoudont@synopsys.com
    Changed at Thursday, 14-Mar-19 20:50:54 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 48dc9cf87f3a93015ecccad29fcf36d22923a984

    Comments

    [ARC] Add more load/store variants.
    
    On ARC ISA, general format of load instruction is this:
    
        LD<zz><.x><.aa><.di> a, [b,c]
    And general format of store is this:
        ST<zz><.aa><.di> c, [b,s9]
    Where:
    
    <zz> is data size field and can be one of
      <empty> (bits 00) - Word (32-bit), default behavior
      B             (bits 01) - Byte
      H             (bits 10) - Half-word (16-bit)
    
     <.x> is data extend mode:
      <empty> (bit 0) - If size is not Word(32-bit), then data is zero extended
      X       (bit 1) - If size is not Word(32-bit), then data is sign extended
    
     <.aa> is address write-back mode:
      <empty> (bits 00) - no write-back
      .AW  (bits 01) - Preincrement, base register updated pre memory transaction
      .AB  (bits 10) - Postincrement, base register updated post memory transaction
    
     <.di> is cache bypass mode:
      <empty> (bit 0) - Cached memory access, default mode
      .DI     (bit 1) - Non-cached data memory access
    
      This patch adds these load/store instruction variants to the ARC backend.
    
    Patch By Denis Antrushin! <denis@synopsys.com>
    
    Differential Revision: https://reviews.llvm.org/D58980
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356200 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/ARC/ARCInstrFormats.td
    • lib/Target/ARC/ARCInstrInfo.cpp
    • lib/Target/ARC/ARCInstrInfo.h
    • lib/Target/ARC/ARCInstrInfo.td
    • test/MC/Disassembler/ARC/ldst.txt