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Revision 1a446d1577d734d7e8f3e67ab8c72e9b6ced9a17

Infra

Steps and Logs

Show:
  1. ( 5 ms ) setup_build

    running recipe: “wasm_llvm”

  2. ( 16 secs ) bot_update

    [4GB/290GB used (1%)]

  3. ( 1 hrs 47 mins ) annotated steps
  4. ( 0 ) Clobbering work dir
  5. ( 27 mins 46 secs ) Sync Repos
  6. ( 2 mins 35 secs ) LLVM
  7. ( 9 mins 18 secs ) LLVM regression tests
  8. ( 58 secs ) V8
  9. ( 13 secs ) jsvu
  10. ( 10 secs ) WABT
  11. ( 41 secs ) binaryen
  12. ( 2 mins 48 secs ) fastcomp
  13. ( 30 secs ) emscripten
  14. ( 2 mins ) emscripten (asm2wasm)
  15. ( 1 mins 10 secs ) emscripten (emwasm)
  16. ( 10 secs ) musl
  17. ( 1 secs ) compiler-rt
  18. ( 15 secs ) libcxx
  19. ( 13 secs ) libcxxabi
  20. ( 1 mins 49 secs ) Archive binaries
  21. ( 6 mins 55 secs ) Debian package
  22. ( 16 secs ) Compile LLVM Torture (O0)
  23. ( 2 secs ) Execute LLVM Torture (validate, O0)
  24. ( 19 secs ) Compile LLVM Torture (O2)
  25. ( 2 secs ) Execute LLVM Torture (validate, O2)
  26. ( 15 secs ) Link LLVM Torture (lld, O0)
  27. ( 12 secs ) Link LLVM Torture (lld, O2)
  28. ( 11 secs ) Execute LLVM Torture (d8, O0)
  29. ( 10 secs ) Execute LLVM Torture (d8, O2)
  30. ( 3 mins 47 secs ) Compile LLVM Torture (asm2wasm, O0)
  31. ( 8 mins 10 secs ) Compile LLVM Torture (asm2wasm, O3)
  32. ( 11 secs ) Execute LLVM Torture (asm2wasm, O0)
  33. ( 4 secs ) Execute LLVM Torture (asm2wasm, O3)
  34. ( 2 mins 27 secs ) Compile LLVM Torture (emwasm, O0)
  35. ( 7 mins 7 secs ) Compile LLVM Torture (emwasm, O3)
  36. ( 8 secs ) Execute LLVM Torture (emwasm, O0)
  37. ( 5 secs ) Execute LLVM Torture (emwasm, O3)
  38. ( 15 mins 30 secs ) Execute emscripten testsuite (emwasm)
  39. ( 10 mins 31 secs ) Execute emscripten testsuite (asm2wasm)
  40. ( 1 secs ) Execute emscripten wasm simd
  41. ( 20 secs ) Summary
  42. ( 0 ) recipe result

Timing

Create Thursday, 14-Mar-19 18:03:55 UTC
Start Thursday, 14-Mar-19 18:04:16 UTC
End Thursday, 14-Mar-19 19:52:47 UTC
Pending 21 secs
Execution 1 hrs 48 mins

Tags

KeyValue
buildset commit/git/1a446d1577d734d7e8f3e67ab8c72e9b6ced9a17
buildset commit/gitiles/llvm.googlesource.com/llvm/+/1a446d1577d734d7e8f3e67ab8c72e9b6ced9a17
scheduler_invocation_id 9084418693923938000
scheduler_job_id wasm/linux
user_agent luci-scheduler

Input Properties

NameValue
$recipe_engine/runtime { "is_experimental": false, "is_luci": true }
branch "refs/heads/master"
buildername "linux"
buildnumber 4005
mastername "client.wasm.llvm"
repository "https://llvm.googlesource.com/llvm"
revision "1a446d1577d734d7e8f3e67ab8c72e9b6ced9a17"

Output Properties

NameValue
$recipe_engine/path { "cache_dir": "/b/swarming/w/ir/cache", "temp_dir": "/b/swarming/w/ir/tmp/rt" }
$recipe_engine/runtime { "is_experimental": false, "is_luci": true }
bot_id "swarm2469-c4"
branch "refs/heads/master"
buildername "linux"
buildnumber 4005
got_revision "1c2fa0fdda124fad7f41d30d19efb901df7e4408"
got_waterfall_revision "b0d7ba40c108aa169f37e023454e828dc737a0ed"
mastername "client.wasm.llvm"
path_config "generic"
recipe "wasm_llvm"
repository "https://llvm.googlesource.com/llvm"
revision "1a446d1577d734d7e8f3e67ab8c72e9b6ced9a17"

All Changes

  1. [GlobalISel][AArch64] Add partial selection support for G_INSERT_VECTOR_ELT

    Changed by Jessica Paquette - jpaquetteohnoyoudont@apple.com
    Changed at Thursday, 14-Mar-19 18:01:30 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 1a446d1577d734d7e8f3e67ab8c72e9b6ced9a17

    Comments

    [GlobalISel][AArch64] Add partial selection support for G_INSERT_VECTOR_ELT
    
    This adds support for inserting elements into packed vectors. It also adds
    two tests: one for selection, and one for regbank select.
    
    Unpacked vectors will come in a follow-up.
    
    Differential Revision: https://reviews.llvm.org/D59325
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356182 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/AArch64/AArch64InstructionSelector.cpp
    • lib/Target/AArch64/AArch64LegalizerInfo.cpp
    • lib/Target/AArch64/AArch64RegisterBankInfo.cpp
    • test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    • test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir
    • test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
  2. Auto-generate an existing test to make it easier to update

    Changed by Philip Reames - listmailohnoyoudont@philipreames.com
    Changed at Thursday, 14-Mar-19 17:59:59 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 751d75d68309ba9fb2ddf49027f0344964ddfa46

    Comments

    Auto-generate an existing test to make it easier to update
    
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356181 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/X86/hoist-invariant-load.ll
  3. [ARC] Better classify add/sub immediate instructions in frame lowering.

    Changed by Pete Couperus - petecoupohnoyoudont@synopsys.com
    Changed at Thursday, 14-Mar-19 17:50:46 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 4385104c44f7189db633f82379f596dae90ff6e9

    Comments

    [ARC] Better classify add/sub immediate instructions in frame lowering.
    
    Summary:
    Some operations have multiple ARC instructions that are applicable.
    For instance, "add r0, r0, 123" can be encoded as a "LImm" instruction
    with a 32-bit immediate (8-bytes), or as a signed 12-bit immediate instruction
    for the case where the source and destination register are the same (4-bytes).
    The ARC assembler will choose the shortest encoding, but we should track
    the correct instruction in the compiler.
    This patch fixes the instruction used in some cases from ARCFrameLowering.
    
    Subscribers: hiraditya, jdoerfert, llvm-commits
    
    Tags: #llvm
    
    Differential Revision: https://reviews.llvm.org/D59326
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356179 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/ARC/ARCFrameLowering.cpp
  4. Speeding up llvm-cov export with multithreaded renderFiles implementation.

    Changed by Max Moroz - mmorozohnoyoudont@chromium.org
    Changed at Thursday, 14-Mar-19 17:49:27 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 3384c56bc0a6b2982282f8850af6c232ec98135e

    Comments

    Speeding up llvm-cov export with multithreaded renderFiles implementation.
    
    Summary:
    CoverageExporterJson::renderFiles accounts for most of the execution time given a large profdata file with multiple binaries.
    
    Proposed solution is to generate JSON for each file in parallel and sort at the end to preserve deterministic output. Also added flags to skip generating parts of the output to trim the output size.
    
    Patch by Sajjad Mirza (@sajjadm).
    
    Reviewers: Dor1s, vsk
    
    Reviewed By: Dor1s, vsk
    
    Subscribers: liaoyuke, mgrang, jdoerfert, llvm-commits
    
    Tags: #llvm
    
    Differential Revision: https://reviews.llvm.org/D59277
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356178 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • docs/CommandGuide/llvm-cov.rst
    • test/tools/llvm-cov/export_functions.test
    • test/tools/llvm-cov/showExpansions.cpp
    • tools/llvm-cov/CodeCoverage.cpp
    • tools/llvm-cov/CoverageExporterJson.cpp
    • tools/llvm-cov/CoverageViewOptions.h
  5. [InstCombine] add tests for funnel shift constant shift amount mod bitwidth; NFC

    Changed by Sanjay Patel - spatelohnoyoudont@rotateright.com
    Changed at Thursday, 14-Mar-19 17:39:40 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 587de2cafa83c6b8589655dcf77f9b7cf0bd3bc5

    Comments

    [InstCombine] add tests for funnel shift constant shift amount mod bitwidth; NFC
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356175 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/Transforms/InstCombine/fsh.ll
  6. [Tests] Add tests for reordering of unordered atomics on invariant locations

    Changed by Philip Reames - listmailohnoyoudont@philipreames.com
    Changed at Thursday, 14-Mar-19 17:36:58 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 4411e545d04a718904059d75a0cabbc226dc2788

    Comments

    [Tests] Add tests for reordering of unordered atomics on invariant locations
    
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356172 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/X86/atomic-unordered.ll
  7. Allow code motion (and thus folding) for atomic (but unordered) memory operands

    Changed by Philip Reames - listmailohnoyoudont@philipreames.com
    Changed at Thursday, 14-Mar-19 17:20:59 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 7747c1d2df876168611373f39f8513701f77e777

    Comments

    Allow code motion (and thus folding) for atomic (but unordered) memory operands
    
    Building on the work done in D57601, now that we can distinguish between atomic and volatile memory accesses, go ahead and allow code motion of unordered atomics. As seen in the diffs, this allows much better folding of memory operations into using instructions. (Mostly done by the PeepholeOpt pass.)
    
    Note: I have not reviewed all callers of hasOrderedMemoryRef since one of them - isSafeToMove - is very widely used. I'm relying on the documented semantics of each method to judge correctness.
    
    Differential Revision: https://reviews.llvm.org/D59345
    
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356170 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/CodeGen/MachineInstr.cpp
    • test/CodeGen/X86/atomic-non-integer.ll
    • test/CodeGen/X86/atomic-unordered.ll
  8. [Tests] Add negative folding tests w/fences as requested in D59345

    Changed by Philip Reames - listmailohnoyoudont@philipreames.com
    Changed at Thursday, 14-Mar-19 17:05:18 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 3b4378582808382fd4abfb57b51ec6e2ce77ee4c

    Comments

    [Tests] Add negative folding tests w/fences as requested in D59345
    
    
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356165 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • test/CodeGen/X86/atomic-unordered.ll
  9. [X86] Fix the pattern changes from r356121 so that the ROR*r1/ROR*m1 pattern use the rotr opcode.

    Changed by Craig Topper - craig.topperohnoyoudont@intel.com
    Changed at Thursday, 14-Mar-19 16:53:24 UTC
    Repository https://llvm.googlesource.com/llvm
    Branch
    Revision 13b61457d35a5d694e994b5b2e5050a11199af9a

    Comments

    [X86] Fix the pattern changes from r356121 so that the ROR*r1/ROR*m1 pattern use the rotr opcode.
    
    These instructions used to use rotl with a bitwidth-1 immediate. I changed the immediate to 1,
    but failed to change the opcode.
    
    Thankfully this seems to have not caused a functional issue because we now had two rotl by 1 patterns,
    but the correct ones were earlier and took priority. So we just missed some optimization.
    
    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356164 91177308-0d34-0410-b5e6-96231b3b80d8
    

    Changed files

    • lib/Target/X86/X86InstrShiftRotate.td
    • test/CodeGen/X86/funnel-shift-rot.ll
    • test/CodeGen/X86/rot32.ll
    • test/CodeGen/X86/rot64.ll